According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.

A first conductive structure forms a gate electrode of a first transistor of a first transistor type. A second conductive structure forms gate electrodes of both a second transistor of the first transistor type and a first transistor of a second transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms gate electrodes of both a third transistor of the first transistor type and a third transistor of the second transistor type. Gate electrodes of the first and second transistors of the first transistor type are separated by a fixed pitch, as are the gate electrodes of the second and third transistors of the second transistor type. The gate electrodes of the first transistor of the first transistor type and the second transistor of the second transistor type are separated by at least the fixed pitch.

A layout structure of a standard cell using a complementary FET (CFET) is provided. First and second transistors that are three-dimensional transistors lie between first and second power supply lines as viewed in plan, the second transistor being formed above the first transistor in the depth direction. A first local interconnect is connected with the source or drain of the first transistor, and a second local interconnect is connected with the source or drain of the second transistor. The first and second local interconnects extend in the Y direction, overlap each other as viewed in plan, and both overlap the first and second power supply lines as viewed in plan.

Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.

Provided is a semiconductor device including a substrate, a lower power line disposed on a lower portion of the substrate, a channel pattern, on the substrate, including a plurality of semiconductor patterns spaced apart from each other and stacked, a source/drain pattern connected to the channel pattern, a gate electrode between the substrate and each of the plurality of semiconductor patterns, and a rear surface filler structure penetrating the substrate to be disposed under the gate electrode. The rear surface filler structure includes a first filler pattern adjacent to the gate electrode, and a second filler pattern disposed under the first filler pattern. The first filler pattern covers an upper surface of the second filler pattern and a portion of each of side surfaces of the second filler pattern.

A semiconductor device includes a substrate including a first active pattern and a second active pattern that are spaced apart from each other in a first direction that is parallel to a top surface of the substrate, a first source/drain pattern on the first active pattern, a second source/drain pattern on the second active pattern, a first active contact on the first source/drain pattern, a second active contact on the second source/drain pattern, and a cutting pattern between the first active contact and the second active contact, where the cutting pattern may include a first cutting pattern between the first active contact and the second active contact, the first cutting pattern extending toward the substrate, and a second cutting pattern on at least one lateral surface of the first cutting pattern and a bottom surface of the first cutting pattern, the second cutting pattern exposing at least a portion of the at least one lateral surface of the first cutting pattern.