An IC device includes cells at cell locations, each cell including a device layer including gates spaced in a first direction according to a gate pitch, first metal lines in a first overlying metal layer, second metal lines in a second overlying metal layer and spaced in the first direction according to a metal line pitch, and a pin including a first metal line coupled to the device layer and a second metal line. A metal line/gate pitch ratio is less than 1, first and second cells correspond to a same IC component and have a same width between lateral edges, the first cell includes the first pin metal line a first distance from a first lateral edge, and the second cell includes the second pin metal line a second distance from the first lateral edge that differs from the first distance by a fraction of the metal line pitch.