An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one metal-short-related failure mode.

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (NCEM). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments (DOEs), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

A semiconductor structure includes a plurality of cells. Each cell has a plurality of transistors, a plurality of inner metal lines, two first backside power lines and one second backside power line. The inner metal lines, the first backside power lines and the second backside power line are disposed on a back side of the transistors. The inner metal lines, the first backside power lines and the second backside power line extend along a first axis. The second backside power line is disposed between the two first backside power lines. The inner metal lines are electrically connected to the first backside power lines and the transistors, and electrically connected to the second backside power line and the transistors. The cells are arranged along a second axis, the second axis being vertical to the first axis.

An integrated circuit includes a plurality of routing lines extending along a first direction, the plurality of routing lines being separated in the first direction by integral multiples of a nominal minimum pitch. The integrated circuit includes a plurality of standard cells, at least one of the plurality of standard cells having a first boundary coinciding with a routing line of the plurality of routing lines, and a second boundary offset from each of the plurality of routing lines.

A semiconductor device includes a substrate; a first transistor on the substrate; a first contact on a source/drain pattern of the first transistor; a second transistor on the substrate; a second contact on a gate electrode of the second transistor; a first connecting structure that includes at least one first wiring and at least one first via that are alternately stacked on the first contact; a second connecting structure that includes at least one second wiring and at least one second via that are alternately stacked on the second contact; a first connecting via on the first connecting structure; a second connecting via on the second connecting structure; and a connecting wiring on the first connecting via and the second connecting via.

An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via. The set of active regions extends in a first direction, and is on a first level. The first contact extends in a second direction, is on a second level, and overlaps at least a first active region. The set of gates extends in the second direction, overlaps the set of active regions, and is on a third level. The first conductive line and the second conductive line extend in the first direction, overlap the first contact, and are on a fourth level. The first via electrically couples the first contact and the first conductive line together. The second via electrically couples the first contact and the second conductive line together.

An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch.

Provided are a semiconductor device and a method of manufacturing the semiconductor device which enable a hard copy of a reconfigurable circuit, which employs a resistance variable element, to be formed at low cost. The method of manufacturing a semiconductor device is for manufacturing a hard copy from a reconfigurable circuit chip that employs a resistance-variable non-volatile element formed inside a multi-layered wiring layer on a semiconductor substrate, wherein the hard copy is manufactured by using a semiconductor substrate base that is the same as that of the semiconductor substrate for forming the reconfigurable circuit chip.

An integrated circuit (IC) comprises first and second conductors in one layer of the IC, wherein the first conductor is oriented along a first direction, the second conductor is oriented along a second direction generally perpendicular to the first direction, and the second conductor is electrically connected to the first conductor. The IC further comprises a third conductor in another layer of the IC, oriented along the second direction, and above the second conductor; a first via connecting the first and third conductors; and a second via connecting the second and third conductors.