An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.

An IC device includes cells at cell locations, each cell including a device layer including gates spaced in a first direction according to a gate pitch, first metal lines in a first overlying metal layer, second metal lines in a second overlying metal layer and spaced in the first direction according to a metal line pitch, and a pin including a first metal line coupled to the device layer and a second metal line. A metal line/gate pitch ratio is less than 1, first and second cells correspond to a same IC component and have a same width between lateral edges, the first cell includes the first pin metal line a first distance from a first lateral edge, and the second cell includes the second pin metal line a second distance from the first lateral edge that differs from the first distance by a fraction of the metal line pitch.

A semiconductor device may include a first impurity pattern and a second impurity pattern spaced apart from each other in a first direction on a substrate, where the first direction may be parallel to an upper surface of the substrate and where the first and second impurity patterns may include impurities having different conductive types; a first semiconductor pattern between the first impurity pattern and the second impurity pattern; and a first gate pattern crossing the first semiconductor pattern. The first gate pattern may include a gate region and an extension region. The gate region may extend in a second direction, which may cross the first direction. The extension region may extend from the gate region in the first direction.

A method includes a first set of active areas extending in a first direction and separated from each other along a second direction in a cell; first and second gate s that cross the first set of active areas along the second direction, the first gate being shared by a first transistor of a first type and a second transistor of a second type and the second gate being shared by a third transistor of the first type and a fourth transistor of the second type; and a set of conductive lines arranged in three metal tracks in the cell and coupling at least one of terminals of the first to fourth transistors to another one of the terminals of the first to fourth transistor. The first transistor is turned off to electrically disconnect a source/drain terminal of the first transistor from a source/drain terminal of the fourth transistor.

A method of fabricating a semiconductor device may include providing a substrate, forming active fin regions, source/drain patterns, gate structures, and an inter-gate insulating layer on the substrate, forming full height contacts, forming full height gate contacts, recessing a first subset of the full height contacts and a second subset of the full height gate contacts to form reduced height contacts and reduced height gate contacts, respectively, forming an upper insulating pattern, and forming interconnection patterns on the full height contacts, the full height gate contacts, and the upper insulating pattern.

A device includes a first gate structure, a second gate structure, a third gate structure and a first conductive segment. The first gate structure corresponds to a control terminal of a first switch. The second gate structure corresponds to a control terminal of a second switch. The third gate structure corresponds to a control terminal of a third switch, and coupled to the first gate structure. The first conductive segment is configured to couple the first switch, the second switch and the third switch to each other, and disposed between the second gate structure and the third gate structure. A distance between the first gate structure and the second gate structure is approximately equal to a distance between the third gate structure and the second gate structure.