The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a non-magnetic transition-metal doped contact silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The non-magnetic transition-metal doped contact silicide layer includes a non-magnetic transition-metal, a first metal, and a silicon containing compound, and includes greater than or about 8.0 E+13 per cm.sup.2 non-magnetic transition-metal atoms. The first metal layer includes the first metal and overlies the non-magnetic transition-metal doped contact silicide layer.

A semiconductor structure includes a Schottky diode structure, which includes: a first trench extending through a first N-type semiconductor layer and being disposed in the first N-type semiconductor layer; a first insulating layer disposed in the first trench; two polysilicon layers or metal silicide layers disposed in the first trench, wherein an upper one and a lower one of the polysilicon layers or metal silicide layers are disposed in parallel; a first P-type protective layer, which is grounded and disposed on a bottom of the first trench, and contacts the first insulating layer and a bottom surface of the lower one of the polysilicon layers or metal silicide layers; a metal layer respectively disposed as a top surface and a lower bottom surface of the semiconductor structure to form a source and a drain as electrodes for the semiconductor structure to be connected to an external device.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a third nitride region. The first nitride region includes Al.sub.x1Ga.sub.1-x1N (0x1<1). The first nitride region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The second nitride region includes Al.sub.x2Ga.sub.1-x2N (x1<x21) or In.sub.yAl.sub.zGa.sub.(1-y-z)N (0<y1, 0z<1, y+z1). The second nitride region includes a sixth partial region. The third nitride region includes Al.sub.x3Ga.sub.1-x3N (x1<x3<x2). The third nitride region includes a seventh partial region.

A semiconductor device includes a semiconductor member, a drain electrode, a gate electrode, a source electrode, and an insulating film. The semiconductor member is provided with a first groove and a second groove. The gate electrode is disposed inside the first groove. The source electrode is disposed inside the second groove. The insulating film is provided on an inner surface of the second groove. The insulating film contains negative fixed charges. A first semiconductor region of the semiconductor member has first conductivity type impurities. A second semiconductor region of the semiconductor member has a higher concentration of the first conductivity type impurities. The second semiconductor region is located on the upper side of the first semiconductor region. The source electrode can form a Schottky junction with the first semiconductor region. The source electrode can form an ohmic junction with the second semiconductor region.

A voltage generation circuit includes a first terminal; a second terminal; a field-effect transistor of a depletion type; a first diode connected between the first terminal and the field-effect transistor; and a first capacitor connected between the field-effect transistor and ground. An anode terminal of the first diode is connected to the first terminal. A cathode terminal of the first diode is connected to a drain terminal of the field-effect transistor. A source terminal of the field-effect transistor is connected to the second terminal and one end of the first capacitor. A gate terminal of the field-effect transistor is connected to another end of the first capacitor.

Circuits, systems, devices, and methods related to transistors with Schottky barriers are discussed herein. For example, a method of fabricating a transistor can include forming a p-well or an n-well in a substrate and forming a gate for the transistor. The method can also include doping a region within the p-well or n-well with a concentration below a threshold and forming a conductor layer on the doped region.

A semiconductor device includes an n-type buried layer, a first N-well region, a p-type body region, a first source/drain region, a second source/drain region, a gate structure, a second N-well region, and a first silicide region. The n-type buried layer in a substrate. The first N-well region is over the n-type buried layer. The p-type body region abuts the first N-well region. The first source/drain region is in the first N-well region. The second source/drain region is in the p-type body region. The gate structure extends across a boundary of the first N-well region and the p-type body region. The second N-well region is over the n-type buried layer. The first silicide region forms a Schottky contact with the second N-well region.

According to one embodiment, a semiconductor device include first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The first conductive member is electrically connected to the second electrode. The first conductive member includes a first conductive portion and a second conductive portion. A first distance between the first electrode and the first conductive portion is shorter than a second distance between the first electrode and the first portion. The semiconductor member is provided between the first electrode and the second electrode.