A method for fabricating an integrated circuit device is provided. The method includes forming a transistor device over a front side of the semiconductor substrate; forming a first contact feature in the semiconductor substrate, wherein the first contact feature is connected with a back side of a first source/drain feature of the transistor device; and forming a memory structure over a back side of the first contact feature facing away from the first source/drain feature.

Device structures and methods of forming the same are provided. A device structure according to the present disclosure includes a substrate having a front side and a back side, a fin structure over the front side, a plurality of nanostructures disposed over the fin structure, a gate structure wrapping around each of the plurality of nanostructures, a first doped region disposed over the back side of the substrate, a backside dielectric layer over the first doped region, and a first contact feature extending through the backside dielectric layer to interface the first doped region.

A semiconductor device including: a first level including a plurality of first metal layers; a second level overlaying the first level, where the second level includes at least one single-crystal silicon layer and a plurality of transistors, where each of the plurality of transistors includes a single-crystal channel, where the second level includes a plurality of second metal layers which includes interconnections between the plurality of transistors, the second level is overlaid by an isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where at least one of the plurality of transistors includes a second single-crystal channel overlaying a first single-crystal channel, where each of at least one of the plurality of transistors includes at least a two sided gate, where the first single-crystal channel is self-aligned to the second single-crystal channel being processed following a same lithography step.

A semiconductor device is provided. The semiconductor device includes source/drain (S/D) epitaxy, a gate stack adjacent to the S/D epitaxy, a semiconductor layer underlying the gate stack and including a semiconductor material surrounded by an inner spacer, an etch stop layer underlying the semiconductor layer, back trench S/D epitaxy and a self-aligned backside contact. The backside trench S/D epitaxy contacts the S/D epitaxy and is insulated from the semiconductor material by the inner spacer. The self-aligned backside contact contacts the backside trench S/D epitaxy and is insulated from the semiconductor material by the etch stop layer.

Integrated circuit dies, systems, and techniques, are described herein related to junction field effect transistors operable at low temperatures and low voltages. A system includes an integrated circuit die deploying a junction field effect transistor that includes a source, a drain, and a gate structure coupled to a multi-layer quantum well. The source and drain are indium arsenide and the gate structure includes a high-k gate dielectric material. The system further includes a cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve a low operating temperature of the integrated circuit die.

An integrated circuit (IC) device includes a front-side interconnect layer, a transistor device, a dielectric layer, a memory structure, and a backside interconnect layer. The transistor device has a gate structure over the front-side interconnect layer. The dielectric layer is over the transistor device. The memory structure is over the dielectric layer. The backside interconnect layer is over the memory structure.

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

Embodiments of the invention disclose semiconductor structures and a method of making the semiconductor structures. According to an embodiment, the semiconductor structure may include a frontside transistor layer having one or more transistors and a backside transistor layer having at least one transistor, the at least one transistor having a recessed channel.

A power semiconductor device includes at a first side and electrically isolated from first and second load terminals, first control electrodes for controlling a load current in first semiconductor channel structures formed in an active region at the first side, and at a second side and electrically isolated from the first and second load terminals, second control electrodes for controlling the load current in second semiconductor channel structures formed in the active region at the second side. At the second side and in a contiguous area of modified control (AMC) belonging to the active region and having a lateral extension of at least 30% of a thickness of a semiconductor body of the device, either no second control electrodes are provided or the second control electrodes are less effective in removing free charge carriers out of the power semiconductor device than the second control electrodes outside the AMC.