An n-type source region and an n-type drain region ND1 are formed in a semiconductor substrate. A gate electrode is formed via a gate insulating film on a portion of the semiconductor substrate located between the source region and the drain region. A p-type impurity region is: formed in a portion of the semiconductor substrate located under the drain region, under the gate electrode, and under the source region. An impurity concentration of the impurity region is higher than an impurity concentration of the semiconductor substrate. The impurity region is spaced apart from an upper surface of the semiconductor substrate.

A high-voltage device includes a substrate, a gate structure over the substrate, a drain region disposed on a first side of the gate structure, a plurality of source regions disposed on a second side of the gate structure, and a plurality of doped regions disposed on the second side of the gate structure. The gate structure includes a plurality of first portions and a plurality of second portions alternately arranged. Width of the first portions are greater than widths of the second portions. The source regions are adjacent to the first portions of the gate structures, and the doped regions are adjacent to the second portions of the gate structure. The drain region and the source regions include dopants of a first conductivity type, and the doped regions include dopants of a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Methods of forming an integrated device, and in particular forming one or more sample wells in an integrated device, are described. The methods may involve forming a metal stack over a cladding layer, forming an aperture in the metal stack, forming first spacer material within the aperture, and forming a sample well by removing some of the cladding layer to extend a depth of the aperture into the cladding layer. In the resulting sample well, at least one portion of the first spacer material is in contact with at least one layer of the metal stack.

The present application discloses a method for making an integrated structure of an MOS transistor having different operation voltages. The resulting integrated structure of an MOS transistor employs a hybrid gate solution. A resulting low voltage MOS transistor adopts a high-K metal gate, so that the gate leakage of the LV (low voltage) MOS transistor can be reduced and speed performance is maintained; and a resulting medium voltage MOS transistor and a high voltage MOS transistor adopt a poly gate, the gate oxide is a single oxide, and a high-K film (HK film) is not present, so that the resulting medium voltage MOS transistor and high voltage MOS transistor are highly reliable without any other reliability problems due to the introduction of a high-K film (HK film) and a gate metal film.

The present disclosure provides for semiconductor devices including field effect transistors. In some embodiments, the semiconductor device includes active structures extending in a first direction on a substrate, an isolation pattern formed in a trench between the active structures, gate structures extending in a second direction across the active structures, a cutting insulation pattern formed between end portions of the gate structures in the second direction, and a lower impurity region at an upper portion of the isolation pattern. A first shape of a lower portion of the cutting insulation pattern disposed under an uppermost surface of the isolation pattern is different from a second shape of a lower portion of the gate structures disposed under the uppermost surface of the isolation pattern. The gate structures are formed on the active structures and the isolation pattern. The lower impurity region contacts at least a portion of the cutting insulation pattern.

A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.

Devices, transistor structures, systems, and techniques are described herein related to silicon on insulator (SOI) substrate integration for gate all around field effect transistors and diode devices. An integrated circuit die includes a diode device having a semiconductor layer, which is on an insulator layer of the SOI substrate, and an integrated gate all around field effect transistor fabricated within a well in the semiconductor layer to form nanoribbons each within a thickness of the semiconductor layer and absent a device subfin.

A method for forming a semiconductor device having a tub. The method includes forming a substrate of a first conductivity type that includes a tub bottom layer of the tub. The tub bottom layer is of a second conductivity type that is opposite to the first conductivity type and has a tub bottom layer peak dopant concentration plane that is substantially away from a top surface of an initial substrate layer of the substrate for a predetermined tub bottom layer buried depth that is essentially greater than 0.5 m. The method can further include forming a plurality of tub sidewalls of the tub. The method can further include forming a high voltage transistor inside the tub.

A semiconductor device includes an epitaxial layer disposed on a substrate, which both have a first conductivity type. A first well region having a second conductivity type is disposed in the epitaxial layer. A gate is disposed on the first well region. A source contact region and a drain contact region both having the first conductivity type are disposed in the first well region. A second well region having the first conductivity type is disposed in the epitaxial layer, laterally abuts the first well region and is in contact with a portion of the substrate. The second well region and the portion of the substrate constitute a resistor that is electrically coupled to a ground terminal. A heavily doped region having the first conductivity type is disposed in the second well region and electrically connected to the source contact region.