A semiconductor device includes a semiconductor layer, a trench with the semiconductor layer being a bottom surface thereof, and an insulating layer covering a surface of the trench. The semiconductor layer includes a first contact region, a second contact region located on a first impurity region in a surface portion of the semiconductor layer and separated from the first contact region, and a second impurity region located on the first impurity region below the second contact region and in contact with both the first impurity region and the second contact region. The first impurity region and the first contact region are separated from each other.

The present disclosure generally relates to a semiconductor device including a p-n junction formed in part by a Zener region. In an example, a semiconductor device includes first and second doped regions both in a semiconductor substrate. The first doped region is doped with a first conductivity type dopant. The first doped region is across first and second lateral regions. The second doped region is doped with a second conductivity type dopant opposite from the first conductivity type dopant. The first and second doped regions form a p-n junction. The second doped region underlies the first doped region in the first lateral region. A peak concentration of the second conductivity type dopant is at a uniform depth across the first lateral region and intersects the first doped region in the second lateral region at a lateral distance from a transition between the first and second lateral regions.

Breakdown diodes and methods of making the same are described. Such a breakdown diode can be fabricated in a semiconductor substrate and have a junction configured to breakdown under a target reverse bias applied across the junctions. The junction is located below the surface of the substrate by a distance suitable for ameliorating mechanical stress impact to the reverse bias breakdown voltage of the junction. Moreover, the junction is located away from an interface causing noise issues.

The present invention provides a Zener diode and a manufacturing method, which includes: a substrate; a buried layer formed on at least a part of a first surface of the substrate; an epitaxial layer formed on at least the buried layer; and a diffusion layer formed on at least the epitaxial layer; wherein there is a distance between the diffusion layer and the buried layer.

A semiconductor substrate includes a p-type substrate region, an n-type buried layer on the p-type substrate region, and a p-type semiconductor layer on the n-type buried layer. A DTI region is formed in a trench that penetrates through the p-type semiconductor layer and the n-type buried layer, reaching the p-type substrate region. A plurality of scallops are formed at a side surface of the trench. A size of each of a plurality of first scallops formed at the side surface of the trench in the p-type semiconductor layer is larger than a size of each of a plurality of second scallops formed at the side surface of the trench in the n-type buried layer.

A Zener diode includes a P+ anode, a poly mesh ring residing on the surface of the semiconductor substrate and surrounding the P+ anode, an N+ cathode residing opposite the poly mesh ring from the P+ anode, an outer spacer on an outer portion of the poly mesh ring adjacent the N+ cathode, and an inner spacer on an inner portion of the poly mesh ring adjacent to the P+ anode. The poly mesh ring may be a polysilicon layer residing upon a TEOS layer. The Zener diode may reside in a low dope N-well with a Zener junction including a N-well high region adjacent and below the P+ anode. The Zener diode may reside in a high dope N-well with a Zener junction including a P structure formed in the high dope N-well in an upper portion of the semiconductor substrate and adjacent and surrounding the P+ anode.

A flip-chip diode structure is provided, which comprises: a substrate, two junction regions, two metal electrodes and a dielectric layer. The substrate includes two arc recesses, respectively disposed at opposite edges of the substrate. The two junction regions are disposed within the substrate. Two metal electrodes are disposed on the same side of the substrate and each electrically connected to one of the two junction regions. The dielectric layer covers the arc recesses and the top surface of the substrate between the two metal electrodes. Each of the arc recesses is adjacent to the outer side of one of the metal electrodes, and the maximum depth of the two junction regions within the substrate is less than the depth of the arc recesses.