An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

An integrated circuit includes a first horizontal conductor and a second horizontal conductor. The integrated circuit includes a first diode between a first first-type block and a first second-type block, a second diode between a second first-type block and a second second-type block, and a third diode between a third first-type block and a third second-type block. The first first-type block and the first second-type block are aligned along a first column. The second first-type block and the second second-type block are aligned along a second column. The third first-type block and the third second-type block are aligned along a third column. The second first-type block is connected to the first second-type block through the second horizontal conductor. The third first-type block is conductively connected to the second second-type block through the first horizontal conductor.

The present specification discloses a semiconductor device including dual trenches and a method of fabricating the same. The semiconductor device includes a first region where a plurality of first semiconductor elements are provided on a substrate, a second region where a plurality of second semiconductor elements are provided on the substrate, an isolation region provided in the substrate between the first region and the second region, shallow trenches formed in the substrate of the first region and the second region, a shallow trench insulating film formed inside each of the shallow trenches, a deep trench formed in the substrate of the isolation region, and a deep trench insulating film formed inside the deep trench, in which a well tap structure is not provided in the substrate between the first region and the second region.

A quasi-vertical JBS diode and a monolithic integrated three-phase DRU are provided. The quasi-vertical JBS diode includes a Si substrate, a N+ GaN conductive layer and an N-type GaN drift layer sequentially disposed from bottom to top. A top region of the N-type GaN drift layer defines groove structures distributed concentrically and annularly, and a Mg-doped P-type BN material is disposed on an inside of each of the groove structures and a side of the N-type GaN drift layer. An anode is disposed on a surface of the N-type GaN drift layer defining the groove structures. A cathode is disposed on a surface of the N+ GaN conductive layer at intervals around the N-type GaN drift layer. The monolithic integrated three-phase DRU includes three AC input terminals, two rectified DC output terminals and diode groups corresponding to six rectifier bridge arms. The diodes each are the quasi-vertical JBS diode.

A manufacture includes a polysilicon structure over a portion of a substrate. The manufacture further includes a spacer on a sidewall of the polysilicon structure, wherein the spacer has a concave corner region between an upper portion and a lower portion, the spacer has an outer sidewall and an inner sidewall, and the inner sidewall is between the outer sidewall and the polysilicon structure. The manufacture further includes a protective layer exposing a portion of the outer sidewall of the spacer above the concave corner region, wherein the protective layer covers an entirety of the lower portion of the spacer, and the protective layer directly contacts the substrate.