A semiconductor device includes a compound semiconductor channel layer disposed on a substrate and located in an active element region and a passive element region. A compound semiconductor barrier layer is stacked on the compound semiconductor channel layer and located in the active element region and the passive element region. A source electrode, a gate electrode and a drain electrode are disposed on the compound semiconductor barrier layer and located in the active element region to construct a high electron mobility transistor. In addition, a first terminal electrode, an intermediate electrode and a second terminal electrode are disposed on the compound semiconductor barrier layer and located in the passive element region to construct a resistor.

A semiconductor device includes a compound semiconductor channel layer disposed on a substrate and located in an active element region and a passive element region. A compound semiconductor barrier layer is stacked on the compound semiconductor channel layer and located in the active element region and the passive element region. A source electrode, a gate electrode and a drain electrode are disposed on the compound semiconductor barrier layer and located in the active element region to construct a high electron mobility transistor. In addition, a first terminal electrode, an intermediate electrode and a second terminal electrode are disposed on the compound semiconductor barrier layer and located in the passive element region to construct a resistor.

An example integrated circuit (IC) includes a semiconductor substrate having a first well and a second well; a first resistor disposed on the semiconductor substrate over the first well within a boundary thereof; a second resistor disposed on the semiconductor substrate over the second well within a boundary thereof, the boundary of the second well disjoint from the boundary of the first well; and a first contact to bias the semiconductor substrate at a first voltage, a second contact to bias the first well at a second voltage, and a third contact to bias the second well at a third voltage.