The semiconductor device includes an n-type first semiconductor region 11 formed on a surface side of a p-type semiconductor substrate 10 and serving as a common path for currents flowing through a switching element and a protection element, an n-type common contact region 12 formed on the first semiconductor region 11 with a high impurity concentration and connected to a common electrode 21 serving as both a first main electrode and a protection element side first electrode, a p-type second semiconductor region 13 and a p-type third semiconductor region 14 locally formed in the first semiconductor region 11 at locations separated from the common contact region 12, and an n-type fourth semiconductor region 15 locally formed in the second semiconductor region 13 in plan view. A second main electrode 22 is connected to the fourth semiconductor region 15, and a protection element side second electrode 26 is provided inside the third semiconductor region 14.

Disclosed is a high-voltage device with ESD robustness. The high-voltage device is formed on a surface of a semiconductor substrate of a first type. A deep well of a second type opposite to the first type is formed on the surface. A filed isolation layer on the surface separates a drain active region from a source active region, and a control gate on top of the field isolation layer serves as a gate electrode of the high-voltage device. A first well of the second type at least partially overlaps the source active region, extends below the field isolation layer and at least partially overlaps the control gate. A buried layer of the first type at a bottom of the deep well has an extensive portion below the control gate. The deep well provides a conductive channel allowing current to flow from the drain active region to the source active region.

The semiconductor device includes an n-type first semiconductor region 11, and an n-type common contact region 12 formed locally with a high impurity concentration on the first semiconductor region 11 and connected to a common electrode that serves as both a first main electrode of a switching element and a protection element side first electrode on the protection element side. A p-type second semiconductor region 13 and an n-type third semiconductor region 14 are provided in a switching element region R1. The p-type second semiconductor region 13 is formed in the first semiconductor region 11 at a location separated in the radial direction from the common contact region 12, and the n-type third semiconductor region 14 is formed in the second semiconductor region 13. A second main electrode is connected to the third semiconductor region 14. A p-type fourth semiconductor region 16 is provided in a protection element region R2. The p-type fourth semiconductor region 16 is formed in the first semiconductor region 11 at a location separated in the radial direction from the common contact region 12. A protection element side second electrode is connected to the fourth semiconductor region 16.