A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.

A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

A semiconductor device includes a substrate and a drift layer on the substrate, the drift layer having a first conductivity type. The device includes a first plurality of vertical junction field effect (JFET) subcells and a second plurality of vertical JFET subcells on the drift layer. The first plurality of vertical JFET subcells are connected in parallel to form a first JFET device, and the second plurality of vertical JFET subcells are connected in parallel to form a second JFET device. The second JFET device is connected in anti-series with the first JFET device through the drift layer. The device further includes a first gate electrode and a first current terminal in contact with the first plurality of vertical JFET subcells, and a second gate electrode and a second current terminal in contact with the second plurality of vertical JFET subcells.

A method for fabricating semiconductor devices is disclosed herein. The method includes forming a first gate region extending into a substrate and having at least a vertical portion of a first U-shape, where the first gate region has a first conductive type. The method includes forming a channel region extending into the substrate and having a second U-shape surrounded by the first U-shape, where the channel region has a second conductive type. The method includes forming a pair of first epitaxial structures coupled to end portions of the first gate region, respectively, where the first epitaxial structures have the first conductive type. The method includes forming a pair of second epitaxial structures coupled to end portions of the channel region, respectively, where the second epitaxial structures have the second conductive type. The method includes forming a third epitaxial structure having the first conductive type and surrounded by the second U-shape.

Semiconductor devices are provided that comprise a semiconductor layer structure that comprises a drift region having a first conductivity type and a gate junction region having a second conductivity type, and a gate trench in the semiconductor layer structure. At least a portion of the gate junction region that is on a sidewall of the gate trench may have a tapered shape in a cross-sectional view.

A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.

A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.

An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.

An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.

A semiconductor layout structure includes: active layers, each active layer including a first active area and a second active area arranged adjacent to the first active area, the first active area including first transistor areas spaced apart from each other, the second active area including second transistor areas spaced apart from each other; and gate layers, each gate layer being arranged above a respective active layer, and including at least one first gate structure extending along a first direction, and second gate structures spaced apart from each other in the first direction, and the at least one first gate structure and the second gate structures being arranged adjacent to each other, the at least one first gate structure corresponding to the first transistor areas, and each second gate structure corresponding to a second transistor area.