A method of manufacturing a nitride semiconductor device is provided, comprising: forming, on a substrate, a first laminated body where a first nitride semiconductor layer, a second nitride semiconductor layer and a third nitride semiconductor layer are laminated in this order; subsequent to the forming, removing a partial region of the third nitride semiconductor layer, subsequent to the removing; implanting ions to the first nitride semiconductor layer from the partial region where the third nitride semiconductor layer is removed at least through the second nitride semiconductor layer; and subsequent to the implanting the ions, annealing the first laminated body.

A structure having high, middle, and low impurity concentration regions disposed from a surface side of a substrate is more suitably manufactured. A method of manufacturing a semiconductor device includes: a first implantation of first conductivity type impurities into a first conductivity type semiconductor substrate from a surface; melting and solidifying a first semiconductor region between a depth and the surface, wherein the depth is deeper than a depth having a peak impurity concentration in an increased region where the impurity concentration was increased in the first implantation, and shallower than a deeper end of the increased region; a second implantation of the impurities from the surface into a region shallower than the depth; and melting and solidifying a region in which the impurity concentration was increased in the second implantation.

A method of producing a plurality of semiconductor chips includes a) providing a carrier substrate having a first major face and a second major face opposite the first major face; b) forming a diode structure between the first major face and the second major face, the diode structure electrically insulating the first major face from the second major face at least with regard to one polarity of an electrical voltage; c) arranging a semiconductor layer sequence on the first major face of the carrier substrate; and d) singulating the carrier substrate with the semiconductor layer sequence into a plurality of semiconductor chips.

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, metal-0, thermally isolated active region, CMOS gate, or combination thereof.

A semiconductor device includes a substrate, a semiconductor layer that is formed on the substrate and includes a pn junction or a hetero-junction, an insulating film that is formed on the semiconductor layer to be in contact with an end of the pn junction or an end of the hetero-junction, and an electrode formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.

An OTP (One-Time Programmable) memory including OTP memory cells that utilize OTP elements fabricated in CMOS FinFET processes. The OTP memory cell can also include at least one selector built upon at least one fin structure that has at least one CMOS gate to divide the fin structure into at least a first and a second active region. The selector can be implemented as a MOS device, dummy-gate diode, or Schottky diode as selector such as by using different types of source/drain implants. The OTP element that can be implemented as polysilicon, silicided polysilicon, CMOS metal gate, any layers of metal as interconnect, or active region. In one embodiment, the OTP element can be a fin structure and can be built upon the same fin structure as the at least one of the selector. By using different source/drain implant schemes on the two active regions, the selector can be turned on as MOS device, MOS device and/or diode, dummy-gate diode, or Schottky diode.

A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn). Epitaxially growing the drift layer includes creating, within the drift layer, a dopant concentration profile (P) of dopants of the first conductivity type along the vertical direction (Z), the dopant concentration profile (P) in the drift layer exhibiting a variation of a concentration of dopants of the first conductivity type along the vertical direction (Z).

According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises depositing a transition layer on a substrate, depositing GaN material on the transition layer, forming a contact on the GaN material, depositing a stressor layer on the GaN material, separating the transition layer and the substrate from the GaN material, patterning and removing portions of the GaN material to expose portions of the stressor layer.

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, a first source electrode, a second source electrode, and a drain electrode. The second nitride-based semiconductor layer includes a drift region doped, a first barrier region, and a second barrier region. The first and second barrier regions extend downward from a top surface of the second nitride-based semiconductor layer and are separated from each other by a portion of the drift region. The gate electrode is disposed on the first barrier region. The first source electrode is disposed on the portion of the drift region. The second source electrode is disposed on the second barrier region and is electrically coupled with the first source electrode. The drain electrode is connected to the first nitride-based semiconductor layer.

A carrier substrate includes a first major face and a second major face opposite the first major face. A diode structure is formed between the first major face and the second major face, which diode structure electrically insulates the first major face from the second major face at least with regard to one polarity of an electrical voltage.