A multilayered semiconductor diode device can include a substrate including silicon carbide (SiC) with an epitaxial drift layer including a first semiconductor oxide material above the SiC substrate with respect to a growth direction. The multilayered semiconductor diode device can further include a polar nitride layer including a polar semiconductor nitride material above the epitaxial drift layer with respect to the growth direction, and a metal layer above the polar nitride layer with respect to the growth direction.

A diode includes a stack of semiconductor layers and an active area arranged within the stack. The stack includes a lateral surface. The diode includes a first passivation layer and a second passivation layer, the first passivation layer being in contact with the lateral surface, and the second passivation layer being in contact with the lateral surface. The second passivation layer is formed partially on the first passivation layer.

In a power semiconductor device, the present disclosure is intended to control tradeoff characteristics while realizing operation in a high-speed side range of the tradeoff characteristics without depending on a carrier lifetime control technique. An n+ cathode layer includes a first n+ cathode layer contacting a second metal layer, and a second n+ cathode layer provided between the first n+ cathode layer and an n buffer layer while contacting the first n+ cathode layer and the n buffer layer. Crystal defect density in the first n+ cathode layer is higher than crystal defect density in the second n+ cathode layer. The n+ cathode layer is absent in an intermediate region and a terminal region.

We herein describe a power semiconductor device having a semiconductor substrate including an active region and an edge termination region surrounding the active region, an edge termination structure located in the edge termination region of the semiconductor substrate, and a plurality of oxide segments located over the upper surface of the edge termination region of the semiconductor substrate, where the plurality of oxide segments are laterally spaced from each other. The power semiconductor device also includes a charge dissipation layer located over the upper surface of the edge termination region of the semiconductor substrate and the plurality of oxide segments, such that the charge dissipation layer is in contact with the upper surface of the semiconductor substrate only at a plurality of interface regions, where the interface regions comprise regions of the semiconductor substrate located laterally between adjacent oxide segments.

A power semiconductor device includes: first and second load terminals at respective front and back sides of a semiconductor body; in the semiconductor body and electrically connected with the first load terminal at the front side within an active region, a doped front side region of a second conductivity type; in the semiconductor body within an edge termination region, a VLD region of the second conductivity type coupled to the doped front side region and having a laterally varying dopant concentration that decreases in a direction from the active region towards a chip edge; at the front side, in the edge termination region, adjacent to the first load terminal and laterally overlapping with the VLD region, an insulation layer; and, above the insulation layer, in the edge termination region and laterally overlapping with the VLD region at least partially, a conductor coupled to a potential of the first load terminal.

This semiconductor device is provided with: a semiconductor layer; a cell that is provided on the semiconductor layer; an insulating film that covers the cell; a main electrode part that is superposed on the insulating film; a temperature-sensitive diode for sensing temperatures, the diode having a first electrode and a second electrode; and a connection electrode for diode, the connection electrode being used for the purpose of connecting the first electrode to the outside. The main electrode part has: a first bonding region to which a first conductive member is bonded; and a second bonding region to which a second conductive member is bonded. When viewed from the thickness direction of the semiconductor layer, the cell is provided on both a first semiconductor region in the semiconductor layer, and a second semiconductor region in the semiconductor layer.