A capacitor structure is described. The capacitor structure includes a substrate; a source/drain region formed in the substrate to form an active area, the active area having an active area width; and at least two gates formed above the substrate. The at least two gates having a gate width. The gate width is configured to be less than the active area width. And, the at least two gates are formed such that the source/drain region is between the two gates to form at least one channel between the two gates.

An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.

A capacitor structure is described. A capacitor structure including a substrate; a source/drain region formed in the substrate to form an active area having an active area width; and a plurality of gates formed above the substrate. The source/drain region having a reflection symmetry. Each of the plurality of gates having a gate width. The gate width is configured to be less than said active area width. And, the plurality of gates are formed to have reflection symmetry.

An inductor component includes a plurality of conductive elements, each formed as an individual patch of conductive material, with the conductive elements arranged in a vertical stack and tightly coupled to one another. Dielectric is disposed between more adjacent conductive elements, the dielectric has a permittivity and is sufficiently thin so as to provide a mutual inductance factor of at least one-half or greater between adjacent ones of the conductive elements. The dielectric is typically thinner than the adjacent conductors.

Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

A combined metal-oxide-semiconductor (MOS) and metal-insulator-semiconductor (MIS) capacitor assembly is provided. The capacitor assembly includes a substrate comprising a semiconductor material; an oxide layer formed on a surface of the substrate; and an insulator layer formed over at least a portion of the oxide layer. The capacitor assembly further includes first and second conductive terminals, and a third terminal connected with the substrate. The oxide layer is connected in series between the substrate and the first conductive layer to form a first capacitor between the first terminal and the third terminal. The insulator layer is connected in series between the substrate and the second conductive layer to form a second capacitor between the second terminal and the third terminal.

A combined metal-oxide-semiconductor (MOS) and metal-insulator- semiconductor (MIS) capacitor assembly, and a method of forming thereof, is provided. The method of forming the capacitor assembly includes steps of forming an oxide layer on a surface of a substrate comprising a semiconductor material; forming an insulator layer over at least a portion of the oxide layer; depositing a first conductive layer over at least a portion of the oxide layer; depositing a second conductive layer over at least a portion of the insulator layer; depositing a first terminal on the first conductive layer; and depositing a second terminal on the second conductive layer.

An integrated circuit device includes a substrate, and a metal-oxide-semiconductor capacitor (MOSCAP) on the substrate. The MOSCAP includes a lower semiconductor device on the substrate, the lower semiconductor device including a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions, and an upper semiconductor device on the lower semiconductor device, the upper semiconductor device including a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions. The lower gate structure is electrically connected to both of the pair of upper source/drain regions.