A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.

A structure and method for guarding a high voltage region at a semiconductor surface from a low voltage region at the semiconductor surface. The structure comprising at least two trenches between the high and low voltage regions to isolate the high voltage region from the low voltage region. The trenches are spaced apart so as to define a sub-region therebetween. To prevent breakdown across the trenches, an intermediate voltage, i.e., of a value between the voltages of the high and low voltage regions, is applied to the sub-region so as to reduce the voltage drop across each trench. Preferably this is achieved by providing an integrated voltage divider circuit that connects between the high and low voltage regions and has an output connected to the sub-region by which the intermediate voltage is applied to the sub-region.

A semiconductor device, such as a gate-all-around field-effect transistor (GAAFET), that can provide advantages in terms of higher operating voltages. The semiconductor device includes a substrate with a p-type well, an n-type well, and a depletion region; an insulating layer disposed on the p-type well; a first epitaxial layer disposed on the insulating layer; a second epitaxial layer disposed on the p-type well, the n-type well, and/or the depletion region; and a gate formed around a channel and between the first epitaxial layer and the second epitaxial layer.

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

A semiconductor device including a semiconductor substrate of a first conductivity type, a plurality of base regions of a second conductivity type formed on a first principal surface of the semiconductor substrate via a semiconductor layer of the first conductivity type, and a plurality of source regions of the first conductivity type formed in the base regions. Each base region, in a top-down view from an angle perpendicular to the first principle surface, is of a polygonal shape. Each adjacent two of the base regions in the top-down view have two sides, one from each of the two base regions, that face each other across a portion of the semiconductor layer, the source region being formed at only one of the two sides.

A semiconductor device provides reduced size and increased performance, and includes a semiconductor layer having a surface layer including first and second semiconductor regions connected to first and second potentials, respectively; a third semiconductor region provided inside the first semiconductor region and connected to a third potential; a fourth semiconductor region provided inside the second semiconductor region and connected to the third potential; a plurality of a first element provided in each of the first, second, third, and fourth semiconductor regions; a first isolation region provided between and in contact with the first and second semiconductor regions, electrically connected to the semiconductor layer, and connected to a fourth potential; and a second isolation region which encloses the periphery of and maintains a withstand voltage of the first and second semiconductor regions. The third and fourth potentials are lower than the second potential, which is lower than the first potential.

An integrated circuit includes a first well of the first conductivity type formed in a semiconductor layer where the first well housing active devices and being connected to a first well potential, a second well of a second conductivity type formed in the semiconductor layer and encircling the first well where the second well housing active devices and being connected to a second well potential, and a buried layer of the second conductivity type formed under the first well and overlapping at least partially the second well encircling the first well. In an alternate embodiment, instead of the buried layer, the integrated circuit includes a third well of the second conductivity type formed in the semiconductor layer where the third well contains the first well and overlaps at least partially the second well encircling the first well.

A semiconductor device includes a semiconductor layer, a plurality of gate trenches, a gate electrode in the plurality of gate trenches, an n.sup.+-type emitter region, a p-type base region, and an n.sup.-type drift region disposed, lateral to each gate trench, a p.sup.+-type collector region, a plurality of emitter trenches formed between the plurality of gate trenches, a buried electrode in the plurality of emitter trenches, and electrically connected with the n.sup.+-type emitter region, and a p-type floating region formed between the plurality of emitter trenches.

A semiconductor device includes a gate pad, a first source pad and a second source pad insulated from each other, a drain pad, a main region, and a sense region for detecting a forward current and a reverse current. The main region and the sense region each include a plurality of unit cells which are in parallel connection, the number of unit cells in the sense region being smaller than the number of unit cells in the main region. A source electrode of any unit cell in the main region is connected to the first source pad, and a source electrode of any unit cell in the sense region is connected to the second source pad.

A semiconductor device includes a semiconductor layer of a first conductivity type, a plurality of first regions that are spaced apart from each other along a first direction by portions of the semiconductor layer, each of the first regions including a first semiconductor region of a second conductivity type, a second region between the first regions in the first direction, the second region including a second semiconductor region of the first conductivity type and a first insulator between the second semiconductor region and the semiconductor layer, and a third region between the first region and the second region, the third region including a third semiconductor region of the first conductivity type and a second insulator.