Patent classifications
H10F71/137
Half-cell photovoltaic modules
The present invention relates a photovoltaic module comprising 126, 138 or 150 back-contact half-cells. In an embodiment, the half-cells are divided into 3 groups of each 2 parallel strings with each string containing of the total number of half-cells. The module comprises an additional row of 6 back-contact half-cells, relative to known half-cell modules.
Method of manufacturing a photovoltaic device
Method of manufacturing a single-side-contacted photovoltaic device (1), comprising the steps of: a) providing a photovoltaically-active substrate (3) defining a plurality of alternating hole collecting zones (3a) and electron collecting zones (3b) arranged in parallel strips; b) depositing a conductive layer (5) across said zones; c) depositing at least one conductive track (9) extending along at least part of each of said zones (3a, 3b); d) selectively forming a dielectric layer (7) on each of said zones (3a, 3b), so as to leave an exposed area free of dielectric at an interface between adjacent zones (3a, 3b); e) etching said conductive layer (5) in said exposed areas; f) applying a plurality of interconnecting conductors (11a, 11b) so as to electrically interconnect at least a portion of said hole collecting zones (3a) with each other, and to electrically interconnect at least a portion of said electron collecting zones (3b) with each other.
Apparatus For Reduction of Solar Cell LID
Reduction of solar wafer LID by exposure to continuous or intermittent High-Intensity full-spectrum Light Radiation, HILR, by an Enhanced Light Source, ELS, producing 3-10 Sols, optionally in the presence of forming gas or/and heating to within the range of from 100 C.-300 C. HILR is provided by ELS modules for stand-alone bulk/continuous processing, or integrated in wafer processing lines in a High-Intensity Light Zone, HILZ, downstream of a wafer firing furnace. A finger drive wafer transport provides continuous shadowless processing speeds of 200-400 inches/minute in the integrated furnace/HILZ. Wafer dwell time in the peak-firing zone is 1-2 seconds. Wafers are immediately cooled from peak firing temperature of 850 C.-1050 C. in a quench zone ahead of the HILZ-ELS modules. Dwell in the HILZ is from about 10 sec to 5 minutes, preferably 10-180 seconds. Intermittent HILR exposure is produced by electronic control, a mask, rotating slotted plate or moving belt.
Low profile camera and vision sensor
A camera configured for a predetermined environment can be made low profile in the following manner. The camera includes an image sensor that has a light sensitive portion that can sense light from the predetermined environment. A substantially opaque mask is disposed above the light sensitive portion of the image sensor and has at least one opening through which the image sensor senses light. The low profile structure of the camera can be realized with substantially transparent material disposed between the substantially opaque mask and the image sensor that has index of refraction that is greater than an index of refraction of the predetermined environment. Accordingly, light through the opening refracts as it passes through the substantially transparent material to the image sensor.
Fast process flow, on-wafer interconnection and singulation for MEPV
A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.
Sensor chip package structure and manufacturing method thereof
A sensor chip package structure and a manufacturing method thereof are provided. The sensor chip package structure includes a substrate, a sensor chip and a wiring layer. The sensor chip is mounted on the substrate and has a top surface and a concave portion concaved from the top surface. The sensor chip has an active region formed on the top surface and the concave portion is located at one side of the active region. The concave portion has a depth of 100 m to 400 m. The wiring layer is disposed on the sensor chip and electrically connected to the active region. At least a portion of the wiring layer extends from the active region along a sidewall of the concave portion to a bottom surface of the concave portion.
ASSEMBLY COMPRISING A PHOTOVOLTAIC MODULE APPLIED TO A CIRCULABLE ZONE
A photovoltaic structure including an assembly of plural photovoltaic cells arranged side by side and electrically connected together, and an assembly encapsulating the plural photovoltaic cells. The encapsulating assembly and assembly of plural photovoltaic cells is situated between first and second layers, and a fixation layer situated between a circulable zone and a photovoltaic module, enabling adherence of the photovoltaic module to the circulable zone. The first layer includes at least one transparent polymer material and plural panels independent of each other, each panel situated facing at least one photovoltaic cell, to form a discontinuous front face of the photovoltaic module, and rigidity of the encapsulating assembly is defined by a Young's modulus of the encapsulation material greater than or equal to 75 MPa at ambient temperature and a thickness of the encapsulating assembly is between 0.4 and 1 mm.
PHOTOVOLTAIC MODULES FOR RIGID CARRIERS
A photovoltaic module including at least a transparent first layer forming a front face of the photovoltaic module to receive a light flux, an assembly of plural photovoltaic cells arranged side by side and connected together electrically, an assembly encapsulating the photovoltaic cells, and a second layer fo ming a rear face of the photovoltaic module. The encapsulating assembly and assembly of photovoltaic cells is located between the first and second layers. The first layer includes at least a transparent polymer material and plural plates independent from one another, each plate located opposite at least one photovoltaic cell, to form a discontinuous front face for the photovoltaic module. Rigidity of the encapsulating assembly is defined by a Young's modulus of the encapsulation material greater than or equal to 75 MPa at ambient temperature and a thickness of the encapsulating assembly is between 0.4 and 1 mm.
Solar cell emitter region fabrication using ion implantation
Methods of fabricating solar cell emitter regions using ion implantation, and resulting solar cells, are described. In an example, a method of fabricating alternating N-type and P-type emitter regions of a solar cell involves forming a silicon layer above a substrate. Dopant impurity atoms of a first conductivity type are implanted, through a first shadow mask, in the silicon layer to form first implanted regions and resulting in non-implanted regions of the silicon layer. Dopant impurity atoms of a second, opposite, conductivity type are implanted, through a second shadow mask, in portions of the non-implanted regions of the silicon layer to form second implanted regions and resulting in remaining non-implanted regions of the silicon layer. The remaining non-implanted regions of the silicon layer are removed with a selective etch process, while the first and second implanted regions of the silicon layer are annealed to form doped polycrystalline silicon emitter regions.
CAPPED SEMICONDUCTOR BASED SENSOR AND METHOD FOR ITS FABRICATION
A method for fabricating semiconductor-based sensor devices and such a sensor device are described. The sensor devices comprise sensors comprising micro- and/or nanostructures which are in communication with the environment surrounding the sensor devices. The method comprises the steps of providing a semiconductor-based device wafer, fabricating a plurality of sensors on the semiconductor-based device wafer (1), providing (102) a capping wafer, attaching a first side of the capping wafer on the device wafer with each sensor arranged below a recess. The capping wafer comprises, between the recesses, a plurality of holes extending from the second side, wherein the holes are in fluid communication with the cavities by passages arranged between contact areas when the capping wafer has been attached to the device wafer. The method comprises the steps of injecting a liquid into the passages and the holes, forming, from the liquid, a gas permeable segment in the passages, and dividing the device wafer and the attached capping wafer into individual devices along lines through the holes.