Provided is a semiconductor device including: a transistor portion; a current sensing portion which detects a current flowing through the transistor portion; a gate pad which is provided above a semiconductor substrate; and a resistance adjustment portion which is electrically connected to the gate pad and adjusts gate resistances of the transistor portion and the current sensing portion, in which the resistance adjustment portion includes a main adjustment portion which is electrically connected to a gate conductive portion of the transistor portion, and a sense adjustment portion which is electrically connected to a gate conductive portion of the current sensing portion, and each of the main adjustment portion and the sense adjustment portion includes a diode element portion including a plurality of diodes provided in anti-parallel and a resistance portion which is connected to the diode element portion.

A semiconductor device includes a first substrate having opposite first and second sides, a first conductive layer on the first side of the first substrate, and a second substrate having opposite first and second sides. The second side of the second substrate is over the first side of the first substrate. The second substrate includes a semiconductor material, and a Schottky diode electrically coupled to the first conductive layer. The Schottky diode is configured by a first doped region in a first portion of the semiconductor material and a first contact structure. The first doped region contains a dopant at a concentration different from a remainder of the first portion of the semiconductor material to form a Schottky contact with the first contact structure.

A semiconductor device includes a first substrate having opposite first and second sides, a first conductive layer on the first side of the first substrate, and a second substrate having opposite first and second sides. The second side of the second substrate is bonded to the first side of the first substrate. The second substrate includes a semiconductor material, and at least one circuit element electrically coupled to the first conductive layer. The at least one circuit element includes at least one of a Schottky diode configured by the semiconductor material and a first contact structure, a capacitor having a first electrode of the semiconductor material, or a resistor of the semiconductor material.

Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.

In a contact hole, a first side surface of an interlayer insulating film is separated from a second side surface of a first conductive film so that a part of an upper surface of the first conductive film is exposed from the interlayer insulating film. In the contact hole, a third side surface of an insulating film is separated from the second side surface of the first conductive film so that a part of the lower surface of the first conductive film is exposed from the insulating film. A plug includes a silicide layer formed on the second side surface of the first conductive film, a barrier metal film formed on the silicide layer, and a second conductive film formed on the barrier metal film.

A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes a first semiconductor layer, a second semiconductor layer, and a metal layer. The first semiconductor layer including a first material having a first bandgap. The second semiconductor layer is disposed on the first semiconductor layer, wherein the second semiconductor layer includes a second material having a second bandgap, and the second bandgap is different from the first bandgap. The metal layer overlaps the second semiconductor layer. An interface lattice mismatch (carrier channel) is formed between the first semiconductor layer and the second semiconductor layer.

The present application discloses a semiconductor device including a first isolation structure, a second isolation structure, and a third isolation structure disposed in a semiconductor substrate. The semiconductor device further includes a transistor and a resistor. The transistor is disposed between the first isolation structure and the second isolation structure, and includes a gate electrode and a first source/drain (S/D) region. The resistor is disposed between the second isolation structure and the third isolation structure, and includes a resistor electrode. The first S/D region is disposed between the gate electrode and the second isolation structure, and is electrically connected to the resistor electrode.

A semimetal liner and a metal-insulator-metal (MIM) capacitor (MIMCAP) are described along with the methods of manufacture or fabrication. The MIM capacitor structure includes a liner formed of a thin layer or film of a semimetal, which is a few nanometers thick, e.g., a thickness in the range of about 0.5 nm to about 5 nm or more. The semimetal liner is sandwiched between an electrode layer and a dielectric layer, e.g., a layer of high or ultra-high-k material, thereby providing a cap for the electrode to limit leakage currents in the structure.