A semiconductor device includes an insulator layer and a semiconductor layer formed on the insulator layer. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type, and a lightly doped extension region of the first conductivity type separating the first region and the second region along a lateral x-axis. A dielectric structure laterally surrounds the semiconductor layer. At least one of the first region and the lightly doped extension region is formed at a distance to the dielectric structure along a lateral y-axis orthogonal to the x-axis. Along the x-axis and between the second region and the first region, a lateral extension of the semiconductor layer along the y-axis increases with increasing distance to the second region.

An example multigate semiconductor device with varied threshold voltages includes a channel, a source disposed on the channel, a drain disposed on the channel, a first gate disposed on the channel between the source and the drain, and a second gate disposed on the channel between the first gate and the drain. The first gate includes a first metal and the second gate includes a second metal, the second metal being different from the first metal.

A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO.sub.2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

A semiconductor device such as, for example, a gate-all-around field-effect transistor (GAAFET) device suitable for operability under higher operating voltage conditions (e.g., 1.2 volts to 3.3 volts). The semiconductor device includes a first channel that is formed in a first plane of the semiconductor device, a second channel that is formed in a second plane of the semiconductor device different from the first plane, a drain that is formed around the first channel, a gate that is formed around the second channel, and a source that is formed around the second channel.

A transistor structure including a substrate, a gate structure, a first doped region, a second doped region, a drift region, a field plate, a charge storage layer, and a first dielectric layer is provided. The gate structure is located on the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate structure. The drift region is located in the substrate between the gate structure and the second doped region. The field plate is located on the substrate above the drift region. The charge storage layer is located between the field plate and the drift region. The first dielectric layer is located between the field plate and the charge storage layer.

A transistor includes a body region and a drain drift region of opposite first and second conductivity types in a semiconductor layer, as well as a gate dielectric layer including first and second portions of a uniform thickness on the semiconductor layer, wherein the first portion is located over a junction between the body region and the drain drift region and the second portion is located over the drain drift region. The transistor includes a gate electrode on the first portion of the gate dielectric layer, a drain region in the drain drift region and having the second conductivity type, and a field plate located on the second portion of the gate dielectric layer and disposed between the gate electrode and the drain region.