A memory array includes: a plurality of first wires; at least one second wire crossing the first wires; and a plurality of memory elements provided in correspondence with respective intersections of the first wires and the at least one second wire and each having a first electrode and a second electrode arranged spaced apart from each other, a third electrode connected to one of the at least one second wire, and an insulating layer that electrically insulates the first electrode and the second electrode and the third electrode from each other, the first wires, the at least one second wire, and the first wires, the at least one second wire, and the memory elements being formed on a substrate.

A module with a high degree of design flexibility and excellent radiation characteristics is provided. The module includes a multilayer wiring substrate, mounting components mounted on an upper surface of the multilayer wiring substrate, a sealing resin layer sealing the mounting components, a plurality of depressions in an upper surface of the sealing resin layer, and radiators set in the depressions. The mounting components are components whose amounts of heat generated are smaller than those of the mounting components. A gap between a bottom of each of the depressions arranged in a region overlapping each of the mounting components and the mounting component is shorter than a gap between the bottom of each of the depressions arranged in a region overlapping each of the mounting components and the mounting component as seen from a direction perpendicular to the upper surface of the multilayer wiring substrate.

In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

A layered metal oxide field effect material forms a heterojunction from metal oxides with different band gaps, and defines a band gap difference (ΔE)≥1 eV. Band bending is generated at the interface of the heterojunction, such that a potential barrier is formed on the side with the larger band gap and a triangular potential well is formed on the side with the smaller band gap, and under the induction of a gate electric field, a polarized charge is generated at the interface of the heterojunction, and a large number of carriers are accumulated. Therefore, the present layered metal oxide field effect material has high carrier mobility higher than 10.sup.3 cm.sup.2/V.Math.s, and overcomes the problem that the carrier mobility of a conventional metal oxide field effect material is low, it is required to fabricate the metal oxide field effect material into a crystal phase structure with a relatively high cost, and even that a substrate thereof with a crystal phase structure is required.

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including carbon nanotubes (CNTs) embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an interlayer dielectric (ILD) layer is formed over the doped source/drain region and the sacrificial gate structure, a source/drain opening is formed by patterning the ILD layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.

The present disclosure provides fine electrodes in which an organic semiconductor does not easily change with time, and which can be applied to manufacturing of a practical integrated circuit of an organic semiconductor device. The present disclosure relates to electrodes for source/drain of an organic semiconductor device, comprising 10 or more sets of electrodes, wherein a channel length between the electrodes in each set is 200 μm or less, and the electrodes in each set have a surface with a surface roughness Rq of 2 nm or less.

Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.

Provided are a conductive composite structure for an electronic device, a method of preparing the conductive composite structure, an electrode for an electronic device including the conductive composite structure, and an electronic device including the conductive composite structure. The conductive composite structure may contain graphene and an organic composite layer including a conductive polymer having a work function of about 5.3 eV or lower, and has a sheet resistance deviation of about 10% or less.

A method of making a semi-conducting microfiber. The method includes melting a semi-conducting solid polymer material to form a polymer melt, dipping a tip of a tool into the polymer melt, and lifting the tip of the tool away from the polymer melt, forming a microfiber. A semiconducting microfiber. The semiconducting microfiber contains a non-conjugated semiconducting polymer matrix containing crystalline aggregates with intentionally placed conjugation-break spacers along the polymer backbone. A device containing a plurality of semiconducting microfibers. Each of the semiconducting fibers contains a non-conjugated semiconducting polymer matrix containing crystalline aggregates with intentionally placed conjugation-break spacers along the polymer backbone. An apparatus to make a semiconducting microfiber. The apparatus contains a container to melt and hold the molten polymer, a tool dipped into the polymer melt, and a means of lifting tip of the tool away from a surface of the polymer melt forming a microfiber.