A semiconductor device for protecting an internal circuit includes a transistor, a first doping region, and a second doping region. The transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal is coupled to a ground. The source terminal is coupled to the internal circuit. The drain terminal is coupled to an input/output pad. The first doping region has a first conductive type. The second doping region has a second conductive type and is adjacent to the first doping region. The first doping region and the second doping region form the gate terminal. The first conductive type is different from the second conductive type.

The present invention provides an ESD protection circuit including a control circuit, a first transistor, a filter and a second transistor. The control circuit is configured to detect a level of a supply voltage to generate a control signal. The first transistor is coupled between the supply voltage and a ground voltage, and is used to refer to the control signal to determine whether to be enabled as a discharging path for the supply voltage to discharge current to the ground voltage. The filter is configured to filter the control signal to generate a filtered control signal. The second transistor is coupled between the supply voltage and the ground voltage, and is used to refer to the filtered control signal to determine whether to be enabled as a discharging path for the supply voltage to discharge current to the ground voltage.

A pixel substrate includes a photoelectric conversion element. The photoelectric conversion element includes a doped region and a substrate region. The doped region and the substrate region form a pn junction. A pixel circuit is electrically connected to a first supply line and the photoelectric conversion element. A protection circuit is configured to short-circuit the first supply line and the substrate region when a voltage difference between the first supply line and the substrate region falls below a negative threshold voltage.

Devices and methods are disclosed for facilitating faster switching of silicon-based and silicon carbide-based power transistors suitable for use in electric vehicles. The disclosed techniques can minimize the impact on turn-on and turn-off losses, while reducing gate voltage and drain voltage spikes during device switching. A fast/slow cell design incorporating shielded gate MOSFETs controls gate-to-drain capacitance and gate resistances to optimize suppression of voltage overshoot.

A first gate drive outputs a first drive voltage to turn a first transistor on upon occurrence of a condition in which a voltage at a supply terminal is higher than a voltage at a ground terminal, the output first drive voltage being higher than the voltage at the ground terminal. A second gate drive outputs a second drive voltage to turn a second transistor on, upon occurrence of a condition in which the voltage at the supply terminal is lower than the voltage at the ground terminal, the output second drive voltage being higher than the voltage at the supply terminal.

An integrated circuit for power clamping is provided. The integrated circuit for power clamping is electrically coupled to an internal circuit of an integrated circuit through a power line and a ground line, and includes a switch, a first resistor, a capacitor, an inverter and a voltage detection circuit. The voltage detection circuit detects a voltage of the power line, and when the voltage of the power line exceeds a threshold value, the voltage detection circuit electrically connects a first node to the ground line, such that a low potential signal from the ground line is input to the input terminal of the inverter, and then the switch is turned on to form a discharge path.