A power semiconductor device includes: a semiconductor body configured to conduct a forward load current between first and second load terminals; a main control terminal; an auxiliary control terminal isolated from the main control terminal; a control electrode structure including: main control electrodes electrically connected to the main control terminal and configured to control the forward load current, and auxiliary control electrodes electrically connected to the auxiliary control terminal and configured to control an overload current; and an overload structure electrically connected between the second load terminal and the auxiliary control terminal, the overload structure configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control trench electrodes, if a voltage between the first and second load terminals exceeds a maximal value and/or if the voltage between the second load terminal and the auxiliary control terminal is above a breakthrough voltage of the overload structure.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

A MOSFET is provided, including a semiconductor body having a first major surface, a trench extending into the body from the first major surface to a gate region, the body including: a source region of a first conductivity type adjacent a sidewall of the trench at the first major surface, a drain region of the first conductivity type adjacent the trench distant from the source region, and a channel-accommodating region of a second conductivity type opposite to the first conductivity type, adjacent the sidewall of the trench between the source region and the drain region. The semiconductor body includes an Electro Static Discharge (ESD) region of the first conductivity type spaced apart from the trench and extending from the first major surface towards, but not into, the drain region. The ESD region includes a first region of the second conductivity type connected to the gate region.