Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET), forming one or more electrical connections to the FET, forming one or more dielectric layers over at least a portion of the electrical connections, and disposing an electrical element over the one or more dielectric layers, the electrical element being in electrical communication with the FET via the one or more electrical connections. RF device fabrication further involves covering at least a portion of the electrical element with a sacrificial material, applying an interface material over the one or more dielectric layers, the interface material at least partially covering the sacrificial material, and removing at least a portion of the sacrificial material to form a cavity at least partially covered by the interface layer.

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.

A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

Method for fabricating at least one FET transistor (100a, 100b) comprising: fabrication of at least one first semiconducting portion (114) that will form a channel of the FET transistor, fabrication of second semiconducting portions (122, 124, 126) that will be used to form source and drain regions, such that the first semiconducting portion is located between first ends of the second semiconducting portions and such that second ends of the second semiconducting portions opposite the first ends, are in contact with bearing surfaces, and comprising at least one semiconducting material for which the crystalline structure or the atomic organisation, can be modified when a heat treatment is applied to it; heat treatment generating a modification to the crystalline structure of the semiconducting material of the second semiconducting portions and creating a strain (128) in the first semiconducting portion.

A method for fabricating a semiconductor device involves providing a transistor device, forming one or more electrical connections to the transistor device, forming one or more dielectric layers over at least a portion of the electrical connections, applying an interface material over at least a portion of the one or more dielectric layers, removing at least a portion of the interface material to form a trench, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.

A method for fabricating a semiconductor device involves providing a semiconductor substrate, forming an oxide layer in the semiconductor substrate, forming a transistor device over the oxide layer, removing at least part of a backside of the semiconductor substrate, applying a sacrificial material below the oxide layer, covering the sacrificial material with an interface material, and removing at least a portion of the sacrificial material to form a cavity at least partially covered by the interface layer.

A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. The asymmetric spacer assembly is formed by a self-aligned process, resulting in less gate/junction overlap on the drain side of the device and greater gate/junction overlap on the source side of the device. Asymmetric transistors having small gate lengths can be obtained without overlay/misalignment issues.

A method for manufacturing a semiconductor device, including forming a dummy gate structure on a substrate, in which the substrate has a source/drain portion and a channel portion adjacent to the source/drain region, and the dummy gate structure is formed on the channel portion of the substrate; recessing at least a part of the source/drain portion to form a recess in the source/drain portion of the substrate; forming a stress material in the recess; replacing the dummy gate structure with a gate stack; removing the stress material in the recess after the replacing the dummy gate structure with the gate stack; and forming an epitaxy structure in the recess.

A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure.