A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.

Engineered quantum processing elements are disclosed. The engineered quantum processing element includes a dopant dot embedded in a semiconductor substrate. A dielectric material forms an interface with the semiconductor substrate. The dopant dot includes a plurality of dopant atoms and one or more electrons/holes confined within the dopant dot. The geometrical configuration of the plurality of dopant atoms with respect to the semiconductor substrate is engineered to achieve optimal linear hyperfine Stark coefficients. Further, aspects of the present disclosure are directed to methods of fabricating such engineered quantum processing elements.

An object is to increase a tolerance of a gate pulse width in a gate-controlled diode while suppressing detrimental effects on other main electrical characteristics. A gate-controlled diode includes: a diode gate electrode buried in each of first trenches through an oxide film in a first active region; an anode electrode buried in each of second trenches through the oxide film in a second active region; a P type channel layer formed in a surface layer of an N.sup. type semiconductor substrate; and an N.sup.+ type layer formed in a surface layer of the P type channel layer in the first active region. An area of the first active region is 20% or higher and 80% or lower of a sum of the area of the first active region and an area of the second active region.

Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.

One embodiment of the invention provides a method for fabricating a self-aligned gate structure comprising forming at least one first trench having a first width and at least one second trench having a second width in a gate structure comprising a first metallic gate layer. The first width is smaller than the second width. The method comprises depositing at least one conformal dielectric layer on the first metallic gate layer. The dielectric layer completely fills the first trench and partially fills the second trench, such that a portion of the second trench is unfilled. The method comprises depositing a conformal second metallic gate layer on the dielectric layer. The second metallic gate layer fills the unfilled portion of the second trench. The method comprises removing portions of the second metallic gate layer to expose the dielectric layer. Remaining portions of the second metallic gate layer include self-aligned metallic gate electrodes.

A method for manufacturing a semiconductor device includes forming a first insulating layer on a first nitride semiconductor layer having a principal surface, forming a mask including a first mask opening on the first insulating layer, forming a first opening in the first insulating layer through the first mask opening, forming a second nitride semiconductor layer on the first nitride semiconductor layer inside the first opening, forming a second insulating layer covering a boundary between the second nitride semiconductor layer and the first insulating layer through the first mask opening and thereafter removing the mask, forming a second opening in the second insulating layer, forming a first electrode on the second insulating layer contacting the second nitride semiconductor layer through the second opening, and forming a gate electrode above the first nitride semiconductor layer, and separated from the second insulating layer in a plan view perpendicular to the principal surface.

Disclosed is a semiconductor device comprising a substrate including first and second PMOSFET regions, first and second active patterns on the first and second PMOSFET regions, first and second channel patterns on the first and second active patterns and each including semiconductor patterns, and first and second source/drain patterns connected to the first and second channel patterns. The first active pattern includes a first lower semiconductor layer, a first middle semiconductor layer, and a first upper semiconductor layer. Each of the first and second lower semiconductor layers includes silicon. The first middle semiconductor layer includes silicon-germanium. The first middle semiconductor layer has a width that decreases in a downward direction to a maximum value and then increases in the downward direction.

An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first control signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.

Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.

A semiconductor memory device may include a substrate, first and second impurity regions on the substrate, first and second gate insulating layers sequentially stacked on the substrate and extended in a direction between the first and second impurity regions, and a gate electrode on the second gate insulating layer. The first and second impurity regions may have different conductivity types from each other, a bottom surface of the first gate insulating layer may be in direct contact with a top surface of the substrate, and the second gate insulating layer may include a ferroelectric material.