A semiconductor device of embodiments includes an element region, a termination region, and an intermediate region between the element region and the termination region. The element region includes: a silicon carbide layer having a first conductive type silicon carbide region and a second conductive type of silicon carbide regions; and a gate electrode. The intermediate region includes a silicon carbide layer having a second conductive type silicon carbide region outside the second conductive type silicon carbide regions. The width of the second conductive type silicon carbide region in the intermediate region is equal to or more than 0.5 times and equal to or less than 3 times the width of the second conductive type silicon carbide region in the element region.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.

The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.

A semiconductor transistor device includes: a gate trench in a SiC semiconductor body; a channel region at a first side wall of the trench; and a diode region at a second side wall of the trench, the side walls lying opposite to each other in a transverse direction. As seen in a vertical cross-section perpendicular to the side walls, a first surface normal n.sub.1, perpendicular to the first side wall and pointing towards the channel region, is rotated between 174 to 178 in relation to a 4H-SiC Crystal a-direction, and a second surface normal n.sub.2, perpendicular to the second side wall and pointing towards the diode region, is rotated between 2 to 6 in relation to the 4H-SiC Crystal a-direction, or n.sub.1 is rotated between 178 to 182 in relation to a 4H-SiC Crystal m-direction and n.sub.2 is rotated between 2 to 2 in relation to the 4H-SiC Crystal m-direction.

A semiconductor device of embodiments includes an element region and a termination region surrounding the element region. The termination region includes: a silicon carbide layer having a silicon carbide region of a first conductive type, a first silicon carbide region of the second conductive type on the silicon carbide region, and a second silicon carbide region of the second conductive type on the silicon carbide region spaced apart from the first silicon carbide region and surrounding the first silicon carbide region. In the termination region, one contact portion of a wiring layer is connected to the first silicon carbide region, and another contact portion of the wiring layer is connected to the second silicon carbide region. A second conductive type impurity concentration of the first silicon carbide region below the one contact portion is lower than that of the second silicon carbide region below the another contact portion.

A silicon carbide semiconductor device has a first semiconductor region of a first conductivity type, provided in a semiconductor substrate, spanning an active region and a termination region. A second semiconductor region of a second conductivity type is provided between a first main surface and the first semiconductor region, in the active region. A device structure having a first pn junction is provided between the first and second semiconductor regions. An outer peripheral portion of the active region is provided between the first main surface and the first semiconductor region in the active region, and constitutes a second-conductivity-type outer peripheral region that surrounds a periphery of the device structure and forms a second pn junction with the first semiconductor region. A first protective film is provided on the first main surface. The first protective film blocks light generated by a forward current passing through the first and second pn junctions.

A power semiconductor device including an epitaxial layer and a fabrication method thereof. A first well region and a second well region separated from each other respectively extend from a surface of the epitaxial layer into the epitaxial layer. A floating doped region is located in the epitaxial layer and between the first well region and the second well region. The floating doped region is separated from the first well region and the second well region. A first doped region and a second doped region respectively extend from the surface of the epitaxial layer into the first well region and the second well region. A gate structure is located on the epitaxial layer and is adjacent to the first doped region and the second doped region. The gate structure is at least partially overlapped with the floating doped region.

A recovery current is suppressed in a field-effect transistor having a deep layer. In the field-effect transistor, when a semiconductor substrate is viewed from above, contact layers are arranged at interval in a specific direction parallel to trenches in each inter-trench region. When the semiconductor substrate is viewed from above, deep layers are arranged at interval in the specific direction in each inter-trench region. In each inter-trench region, each interval between the contact layers is located above a corresponding one of the deep layers. In each inter-trench region, each interval between the deep layers is located below a corresponding one of the contact layers.

A silicon carbide semiconductor device, including: a semiconductor substrate having first and second main surfaces; a first semiconductor region and a second semiconductor region provided in the semiconductor substrate; third semiconductor regions selectively between the first main surface and the second semiconductor region; a plurality of gate electrodes provided in a plurality of trenches via a plurality of gate insulating films, respectively; second-conductivity-type regions selectively provided between the second semiconductor region and the first semiconductor region; first and second electrodes respectively provided on the first and second main surfaces; a fourth semiconductor region between the first main surface and the first semiconductor region; and a first wiring layer provided on the first main surface. The second-conductivity-type regions includes first second-conductivity-type regions apart from the trenches and in contact with the second semiconductor region. The first semiconductor region includes a first first-conductivity-type region having a different dopant concentration.

In a general aspect, a semiconductor device can include a semiconductor substrate, a trench formed in the semiconductor substrate and a first dielectric layer lining the trench. The semiconductor device can further include a first semiconductor material disposed in a lower portion of the trench. The first dielectric layer being can be disposed between the semiconductor substrate and the first semiconductor material. The semiconductor device can also include a second dielectric layer disposed on the first semiconductor material and a second semiconductor material disposed in an upper portion of the trench. The first dielectric layer can be disposed between the semiconductor substrate and the second semiconductor material. The second dielectric layer can be disposed between the first semiconductor material and the second semiconductor material. The semiconductor device can also include at least one of a diode or a resistor defined in the second semiconductor material.