An IC device includes cells at cell locations, each cell including a device layer including gates spaced in a first direction according to a gate pitch, first metal lines in a first overlying metal layer, second metal lines in a second overlying metal layer and spaced in the first direction according to a metal line pitch, and a pin including a first metal line coupled to the device layer and a second metal line. A metal line/gate pitch ratio is less than 1, first and second cells correspond to a same IC component and have a same width between lateral edges, the first cell includes the first pin metal line a first distance from a first lateral edge, and the second cell includes the second pin metal line a second distance from the first lateral edge that differs from the first distance by a fraction of the metal line pitch.

A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, and placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit, and includes a first and second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes labelling the first and second pin as a first set of to be connected pins, and designating the first set of to be connected pins as a common group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first set of to be connected pins in the common group of pins together, thereby changing the first circuit to a second circuit.

A cell region (of a device) includes: active regions; gate segments and metal-to-source/drain-region (MD) contacts which are interspersed; via-to-gate (VG) contacts; via-to-MD-contact (VD) contacts; the VG contacts and the VD contacts being aligned correspondingly to alpha tracks extending in the first direction; first routing (RTE) segments aligned correspondingly to the alpha tracks; and first buried power grid segments; and first and second ones of the alpha tracks being adjacent to first and second boundaries of the cell region; at least a third one of the alpha tracks being between the first and second alpha tracks; the first alpha track being free from having any of the VG contacts aligned thereto; and the second alpha track being free from having any of the VD contacts aligned thereto.

An integrated circuit including a first standard cell placed continuously on a row having a first height and a row having a second height different from the first height. The integrated circuit also includes a second standard cell continuously placed on a row having the first height and a row having the second height, a plurality of first power lines formed on boundaries of the plurality of rows and configured to supply a first supply voltage to the standard cells, and a plurality of second power lines formed on boundaries of the plurality of rows and configured to supply a second supply voltage to the standard cells. A placement sequence of the power lines supplying a voltage to the first standard cell being different from a placement sequence of the power lines supplying a voltage to the second standard cell.