Analog circuit devices and methods are provided. An analog circuit device comprises a bottom metal routing layer comprising a plurality of tracks, an analog cell comprising an n-type metal oxide semiconductor (NMOS) active region and a p-type metal oxide semiconductor (PMOS) active region, a plurality of polysilicon layers, and a plurality of metal diffusion layers. In the analog device, the NMOS active region, PMOS active region, plurality of polysilicon layers, and plurality of metal diffusion layers make up a CMOS structure. The device further includes a plurality of guard ring cells surrounding the analog cell and a power rail structure configured to provide connection between the bottom metal routing layer and the analog cell.

A three-dimensional semiconductor device is provided. The three-dimensional semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and lower source/drain patterns connected to the lower channel pattern, a second active region on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, and a gate cutting pattern penetrating the gate electrode, and the gate cutting pattern may have a middle width between an upper surface and a lower surface thereof that is less than an upper width of an upper portion of the gate cutting pattern and a lower width of a lower portion of the gate cutting pattern.

A semiconductor device includes a first circuit cell, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first circuit cell includes a first active area in a first well in a substrate, a second active area in a second well in the substrate, and a first gate structure wrapping around nanostructures in the first active area and the second active area. The first dielectric layer is over the first well. The second dielectric layer is over the first well and the second well. The third dielectric layer is over the second well. The first dielectric layer, the second dielectric layer, and the third dielectric layer are under and in contact with the first gate structure. A thickness of the second dielectric layer is less than thicknesses of the first dielectric layer and the third dielectric layer.

A semiconductor device may include a substrate including a first active pattern and a second active pattern, which are spaced apart from each other in a first direction parallel to a top surface of the substrate, a device isolation layer between the first and second active patterns, a first source/drain pattern disposed on the first active pattern, a second source/drain pattern disposed on the second active pattern, a first active contact disposed on the first and second source/drain patterns, a barrier pattern interposed between the first active contact and the first source/drain pattern and between the first active contact and the second source/drain pattern and extended into a space between the first active contact and the device isolation layer, and an air gap interposed between the first active contact and the barrier pattern. The first active contact may be electrically connected to the first and second source/drain patterns.

Provided is a semiconductor device including: a first fin structure extending in a vertical direction; a second fin structure extending in the vertical direction, wherein the second fin structure is spaced apart from the first fin structure; an etch stop pattern between the first fin structure and the second fin structure; a lower insulating layer in contact with a lower surface of the first fin structure, a lower surface of the second fin structure and a lower surface of the etch stop pattern; a device isolation layer including an interposed portion on the etch stop pattern, between the first fin structure and the second fin structure; a gate electrode overlapping the interposed portion and the first fin structure; a channel structure overlapping the gate electrode; and a source/drain pattern connected to the channel structure. The etch stop pattern includes a different insulating material from the device isolation layer.

A semiconductor device includes a substrate, a first lower pattern on the substrate, and an element isolation film on the substrate and surrounding at least parts of sidewalls of the first lower pattern, wherein at least part of an upper surface of the first lower pattern is inclined relative to an upper surface of the substrate.