Integrated circuits with components for protection from electrostatic discharge are provided. An integrated circuit includes a first common line and a second common line. A first electrostatic discharge line is in electrical communication with the first and second common lines. The first electrostatic discharge line includes a first diode and a first clamping device.

An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

Disclosed are devices and methods related to a CMOS switch for radio-frequency (RF) applications. In some embodiments, the switch can be configured to include a resistive body-floating circuit to provide improved power handling capability. The switch can further include an electrostatic discharge (ESD) protection circuit disposed relative to the switch to provide ESD protection for the switch. Such a switch can be implemented for different switching applications in wireless devices such as cell phones, including band-selection switching and transmit/receive switching.

An electrostatic discharge (ESD) protection control circuit for an output pad of an integrated circuit includes an output driver and a control switch. The output driver, coupled to the output pad, includes a first output transistor for outputting power or signals to the output pad. The control switch, for improving ESD protection on the output pad when closed, includes a first connection terminal, coupled to a gate terminal of the first output transistor; a second connection terminal, coupled to a ground terminal; and a control terminal, coupled to a first power supply terminal.

An array substrate and a display panel are provided. The array substrate includes a transparent substrate including a display area and a rim area; a pixel structure and an antistatic switching tube which are arranged on a same side of the transparent substrate. The pixel structure includes a pixel thin-film transistor located in the display area, and the antistatic switching tube is located in the rim area. The pixel structure also includes first grounding wire located on a side of the antistatic switching tube facing away from the transparent substrate, and a second grounding wire located between the antistatic switching tube and the transparent substrate.

Provided is an electrostatic protection circuit that has little leakage current under normal operation and allows a trigger voltage to be set comparatively freely, without requiring a special process step. This electrostatic protection circuit is provided with a series circuit including a transistor, a predetermined number of diodes and an impedance element that are connected in series between the first node and the second node, and a discharge circuit configured to send current from the first node to the second node following an increase in a potential difference that occurs between both ends of the impedance element, when the first node reaches a higher potential than the second node and current flows through the series circuit. The predetermined number of diodes are connected between the source and the back gate of the transistor.

The disclosure provides an ESD protection circuit. The ESD protection circuit comprises: a clamping unit, a driving unit, a resistance unit, a switch unit, and a capacitance unit. The clamping device is coupled between a first power source and a second power source. The driving unit is coupled between the clamping device and a reference node. The resistance unit is coupled between the first power source and the reference node. The switch unit is coupled to the driving unit via the reference node. The capacitance unit is coupled between the switch unit and the second power source. Under a normal operation condition, the driving unit controls the switch unit to be in an un-conducting status. Under an ESD condition, the driving unit controls the switch unit to be in a conducting status.

A first sense resistor is connected between a fourth terminal of a power source potential of a high-potential region and a first terminal of a ground potential. A second sense resistor is connected between a third terminal of a reference potential of the high-potential region and the first terminal. A comparator is disposed in a low-potential region and uses the ground potential as a reference potential for operation. The comparator compares a voltage between an intermediate potential point of the first sense resistor and an intermediate potential point of the second sense resistor with a predetermined reference voltage. The output of the comparator is input through a control circuit and a level shift circuit to a high-side drive circuit driving an upper-arm IGBT. The output of the comparator is input to a driver circuit driving a lower-arm IGBT.

A protection circuit may include a first power line and a second power line, a plurality of high voltage interconnections, a plurality of low voltage interconnections, first and second pickup active regions, a high voltage protection transistor, and a low voltage protection transistor. The first power line and the second power line extending in parallel to each other while facing each other, and a plurality of high voltage interconnections are coupled to the first power line and extend toward the second power line while being spaced apart from each other. The plurality of low voltage interconnections are coupled to the second power line and extend toward the first power line while being spaced apart from each other. The first pickup active region extends across the plurality of high voltage interconnections and the second pickup active region extends across the plurality of low voltage interconnections.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.