H10D62/165

Epitaxial Oxide Integrated Circuit
20250359399 · 2025-11-20 · ·

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a gate oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes an n-type semiconductor layer, a functional layer, a p-type semiconductor layer, a first AlN layer and a first heavily doped n-type semiconductor layer arranged in sequence. The first AlN layer is provided to reduce the diffusion of p-type ions from the p-type semiconductor layer into the first heavily doped n-type semiconductor layer, to avoid a thicker tunneling junction caused by n-type ions/p-type ions co-doping, to improve the tunneling effect of carriers, to enhance the uniformity of the current density distribution of the first heavily doped n-type semiconductor layer injected into the p-type semiconductor layer, to solve the problem that the p-type semiconductor layer has low carrier mobility and high resistivity.

Method to improve performances of tunnel junctions grown by metal organic chemical vapor deposition

A device including an activated p-type layer comprising a III-Nitride based Mg-doped layer grown by vapor phase deposition or a growth method different from MBE. The p-type layer is activated through a sidewall of the p-type layer after the removal of defects from the sidewall thereby increasing a hole concentration in the p-type layer. In one or more examples, the device includes an active region between a first n-type layer and the p-type layer; a second n-type layer on the p-type layer; and a tunnel junction between the second n-type layer and the p-type layer, and the activated p-type layer has a hole concentration characterized by a current density of at least 100 Amps per centimeter square flowing between the first n-type layer and the second n-type layer in response to a voltage of 4 volts or less applied across the first n-type layer and the second n-type layer.