A semiconductor device includes a plurality of tunnel diodes, each of which includes a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type that is provided above the first semiconductor region, the second semiconductor region being a nanowire shape; an insulating film provided around a side surface of the second semiconductor region; a plurality of first electrodes, each coupled to the first semiconductor region; and a plurality of second electrodes, each coupled to the second semiconductor region, wherein the second electrode has a first surface that faces the side surface of the second semiconductor region across the insulating film, and a diameter of a second semiconductor region of a first tunnel diode of the plurality of tunnel diodes is different from a diameter of a second semiconductor region of a second tunnel diode.

An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.

An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.

A memory structure includes insulating layers, gate layers, a first doping layer, second doping layers, third doping layers, a columnar channel, a first dielectric layer, second dielectric layers, and a third dielectric layer. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The second doping layers are in direct contact with the first doping layer to form tunnel diodes, in which the second doping layers and the insulating layers are alternately stacked. The third doping layers surround the columnar channel and are connected to the second doping layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the third doping layers and the gate layers. The third dielectric layer is between the columnar channel and the third doping layers.

A memory structure includes insulating layers, gate layers, a first doping layer, second doping layers, third doping layers, a columnar channel, a first dielectric layer, second dielectric layers, and a third dielectric layer. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The second doping layers are in direct contact with the first doping layer to form tunnel diodes, in which the second doping layers and the insulating layers are alternately stacked. The third doping layers surround the columnar channel and are connected to the second doping layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the third doping layers and the gate layers. The third dielectric layer is between the columnar channel and the third doping layers.

A memory structure includes insulating layers, gate layers, a first doping layer, second doping layers, third doping layers, a columnar channel, a first dielectric layer, second dielectric layers, and a third dielectric layer. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The second doping layers are in direct contact with the first doping layer to form tunnel diodes, in which the second doping layers and the insulating layers are alternately stacked. The third doping layers surround the columnar channel and are connected to the second doping layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the third doping layers and the gate layers. The third dielectric layer is between the columnar channel and the third doping layers.

An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.

An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.

A SRAM cell structure includes a plurality of transistors, a set of contacts, a word-line, a bit-line, a VDD contacting line and a VSS contacting line. The plurality of transistors include n transistors, wherein n is a positive integral less than 6. The set of contacts are coupled to the plurality of transistors. The word-line is electrically coupled to the plurality of transistors. The bit-line and a bit line bar are electrically coupled to the plurality of transistors. The VDD contacting line is electrically coupled to the plurality of transistors. The VSS contacting line is electrically coupled to the plurality of transistors. Wherein as a minimum feature size of the SRAM cell structure gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of the minimum feature size () is the same or substantially the same.

A SRAM cell structure includes a plurality of transistors, a set of contacts, a word-line, a bit-line, a VDD contacting line and a VSS contacting line. The plurality of transistors include n transistors, wherein n is a positive integral less than 6. The set of contacts are coupled to the plurality of transistors. The word-line is electrically coupled to the plurality of transistors. The bit-line and a bit line bar are electrically coupled to the plurality of transistors. The VDD contacting line is electrically coupled to the plurality of transistors. The VSS contacting line is electrically coupled to the plurality of transistors. Wherein as a minimum feature size of the SRAM cell structure gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of the minimum feature size () is the same or substantially the same.