The resistor structure of the semiconductor device according to the embodiment may include a semiconductor substrate including a device semiconductor layer and a resistor semiconductor layer, a first isolation region of device and a second isolation region of device respectively disposed on the device semiconductor layer and the resistor semiconductor layer, and a register poly layer disposed on a first register trench from which a portion of the second isolation region of device is removed.

Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.

In a contact hole, a first side surface of an interlayer insulating film is separated from a second side surface of a first conductive film so that a part of an upper surface of the first conductive film is exposed from the interlayer insulating film. In the contact hole, a third side surface of an insulating film is separated from the second side surface of the first conductive film so that a part of the lower surface of the first conductive film is exposed from the insulating film. A plug includes a silicide layer formed on the second side surface of the first conductive film, a barrier metal film formed on the silicide layer, and a second conductive film formed on the barrier metal film.

The present application discloses a semiconductor device including a first isolation structure, a second isolation structure, and a third isolation structure disposed in a semiconductor substrate. The semiconductor device further includes a transistor and a resistor. The transistor is disposed between the first isolation structure and the second isolation structure, and includes a gate electrode and a first source/drain (S/D) region. The resistor is disposed between the second isolation structure and the third isolation structure, and includes a resistor electrode. The first S/D region is disposed between the gate electrode and the second isolation structure, and is electrically connected to the resistor electrode.

A semiconductor device includes a semiconductor substrate into which a first impurity of an n-type is introduced, an epitaxial layer formed on the semiconductor substrate and into which a second impurity of the n-type is introduced, and a semiconductor region of the n-type formed in a portion of the epitaxial layer located under the first portion, into which a third impurity of the n-type is introduced and which has an impurity concentration higher than an impurity concentration of the epitaxial layer.

A junction field-effect transistor device includes an integrated temperature sensor, and a method of making the same is disclosed. A temperature sensor material having a first charge carrier polarity is implanted into an area of semiconductor material having a second charge carrier polarity, with the area being located adjacent to the junction field-effect transistor. The sensor material contains dopants and exhibits an electrical resistance that increases with a number of ionized ones of the dopants. The number of ionized dopants increases with the temperature of the material. First and second electrical terminals are provided spaced-apart on the sensor material for measuring the electrical resistance of the material. The measured electrical resistance may be translated into a temperature value for the junction field-effect transistor.

A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer, and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a planar device region and a non-planar device region, forming fin-shaped structures on the non-planar device region, forming a first shallow trench isolation (STI) around the substrate on the planar device region, forming a second shallow trench isolation (STI) around the fin-shaped structures, forming first gate structures on the substrate of the planar device region, forming second gate structures on the fin-shaped structures, forming a first resistor on the first STI, and forming a second resistor on the second STI.

A nitride semiconductor device is a nitride semiconductor device including an active element and a passive element, and includes: a nitride semiconductor layer divided into an active region and an inactive region in a plan view; and a metal layer in contact with the nitride semiconductor layer in the inactive region. The active element is provided in the active region, and the passive element is provided in the inactive region. The metal layer includes a coherent state or a metamorphic state relative to the nitride semiconductor layer.

A semiconductor device according to one embodiment of the present invention includes a semiconductor substrate, transistors disposed on the semiconductor substrate, gate pads disposed on the semiconductor substrate and disposed at the outside of the transistors, resistors disposed on the semiconductor substrate and electrically connected to at least one of the gate pads, and upper metal layers disposed on the semiconductor substrate and configured to come into contact with the resistors. At least one of the gate pads is electrically connected to a gate electrode of each of the transistors, the gate pads are spaced apart from each other, and at least one of the resistors is an anti-resonance resistor, which is configured to suppress resonance generated by operation of the transistors, is disposed between two gate pads, and is electrically connected to at least one gate pad of the two gate pads through the upper metal layer.