The present application teaches, inter alia, methods and circuits for operating B-TRANs (double-base bidirectional bipolar junction transistors). Base drive circuits provide high-impedance drive to the base contact region on whichever side of the device is (instantaneously) operating as the collector. (B-TRANs, unlike other bipolar junction transistors, are controlled by applied voltage, not applied current.) Control signals operate preferred drive circuits, providing diode-mode turn-on and pre-turnoff operation, and a hard ON state with a low voltage drop (the transistor-ON state). In some (not necessarily all) preferred embodiments, a self-synchronizing rectifier circuit provides an adjustable low voltage for the gate drive circuit. Also, in some preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while monitoring the base current at that terminal, so that no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in B-TRANs.

A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.

A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

The present application teaches, among other innovations, methods and circuits for operating a B-TRAN (double-base bidirectional bipolar junction transistor). A base drive circuit is described which provides high-impedance drive to the base contact region on whichever side of the device is operating as the collector (at a given moment). (The B-TRAN, unlike other bipolar junction transistors, is controlled by applied voltage rather than applied current.) The preferred implementation of the drive circuit is operated by control signals to provide diode-mode turn-on and pre-turnoff operation, as well as a hard ON state with a low voltage drop (the transistor-ON state). In some but not necessarily all preferred embodiments, an adjustable low voltage for the gate drive circuit is provided by a self-synchronizing rectifier circuit. Also, in some but not necessarily all preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while the base current at that terminal is monitored, so that no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in a B-TRAN.

An exemplary biosensor sensor for detecting the presence of a biological material includes an SOI substrate, a lateral BJT formed on at least a portion of the substrate, and a sensing structure formed on at least a portion of an upper surface of the BJT. The BJT includes an emitter region, a collector region and a base region, the base region being formed between the emitter and collector regions and laterally adjacent thereto. The sensing structure includes at least one dielectric layer contacting at least a portion of the base region. The dielectric layer forms a receptacle for confining a biological molecule being tested and is configured to respond to charges in biological molecules, the charges being converted to a sensing signal by the BJT.

A bipolar junction transistor (BJT), which includes a collector layer, a base layer on the collector layer, an emitter layer on the base layer, and a recess region embedded in the collector layer, is disclosed. A base-collector plane is between the base layer and the collector layer. The recess region is may be below the base-collector plane. Further, the recess region and the base layer are a first type of semiconductor material. By embedding the recess region in the collector layer, the recess region and the collector layer form a first P-N junction, which may provide a point of avalanche for the BJT. Further, the collector layer and the base layer form a second P-N junction. By separating the point of avalanche from the second P-N junction, the BJT may avalanche robustly, thereby reducing the likelihood of avalanche induced failures, particularly in silicon carbide (SiC) BJTs.

Bipolar junction transistors including inorganic channels and organic emitter junctions are used in some applications for forming high resolution active matrix displays. Arrays of such bipolar junction transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.