Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

An integrated circuit (IC) structure with a conductive pathway through resistive semiconductor material, e.g., for bipolar transistors, is provided. The IC structure may include a resistive semiconductor material having a first end coupled to a first doped semiconductor material. The first doped semiconductor material has a first doping type. A doped well may be coupled to a second end of the resistive semiconductor material. The doped well has a second doping type opposite the first doping type. A second doped semiconductor material is coupled to the doped well and has the first doping type. The resistive semiconductor material is within a conductive pathway from the first doped semiconductor material to the second doped semiconductor material.

Devices and methods for manufacturing a deep trench capacitor fuse for high voltage breakdown defense. A semiconductor device comprising a deep trench capacitor structure and a transistor structure. The transistor structure may comprise a base, a first terminal formed within the base, and a second terminal formed within the base. The first terminal and the second terminal may be formed by doping the base. The deep trench capacitor structure may comprise a first metallic electrode layer and a second metallic electrode layer. The first terminal may be electrically connected to the first metallic electrode layer, and the second terminal may be electrically connected to the second metallic electrode layer.

Semiconductor devices for high frequency operations are described. The semiconductor devices include a substrate with an epitaxial layer. The epitaxial layer has higher resistivity than the substrate and includes a surface facing away from the substrate. The epitaxial layer includes a shallow trench isolation (STI) structure extended to a first depth from the surface, which is surrounded by a well structure. Underneath the STI structure, the epitaxial layer includes a lightly doped portion exclusive of dopant atoms of the well structure. Moreover, the STI structure includes an inner portion surrounded by a deep trench isolation structure extended to a second depth from the surface, the second depth being greater than the first depth. An integrated circuit component is located above the inner portion of the STI structure.

Devices and methods for manufacturing a deep trench capacitor fuse for high voltage breakdown defense. A semiconductor device comprising a deep trench capacitor structure and a transistor structure. The transistor structure may comprise a base, a first terminal formed within the base, and a second terminal formed within the base. The first terminal and the second terminal may be formed by doping the base. The deep trench capacitor structure may comprise a first metallic electrode layer and a second metallic electrode layer. The first terminal may be electrically connected to the first metallic electrode layer, and the second terminal may be electrically connected to the second metallic electrode layer.

Integrated circuit devices including a bipolar junction transistor (BJT) and/or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.

An electrostatic discharge protection device includes a substrate, a first doping region of a first conductivity type on the substrate, a second doping region of the first conductivity type on the substrate, an epitaxial layer of a second conductivity type between the first doping region and the second doping region, a first diffusion region of the first conductivity type on the first doping region, a second diffusion region of the second conductivity type on the epitaxial layer, a third diffusion region of the first conductivity type on the second doping region, and a fourth diffusion region of the second conductivity type on the first doping region and spaced apart from the first diffusion region. The first diffusion region and the fourth diffusion region are electrically coupled.

An inverter logic circuit includes a bipolar junction transistor and a zener diode. The zener diode is connected between the base of the bipolar junction transistor and ground (or other reference voltage). The zener diode is reverse biased such that a leakage current through the zener diode allows for sufficient current through the emitter-base terminals of the bipolar junction transistor when a voltage is applied across the emitter and base terminals of the bipolar junction transistor to turn the transistor ON in the absence of an external signal to the base. As such the bipolar junction transistor functions as a normally ON bipolar junction transistor.

A transient voltage suppressor is provided, including a semiconductor substrate and a doped well of first conductivity type, an epitaxial layer of second conductivity type, first and second heavily doped regions of second conductivity type, and a third heavily doped region of first conductivity type in the doped well. The first heavily doped region is connected to a fourth heavily doped region of second conductivity type, and the fourth heavily doped region and a fifth heavily doped region of first conductivity type are disposed in the epitaxial layer. A sixth heavily doped region of second conductivity type is disposed in the epitaxial layer and connected in common with the third heavily doped region in the doped well. The fifth and second heavily doped regions are connected to I/O and ground, respectively. When applying a positive surged mode, the disclosed transient voltage suppressor is characterized by providing multiple discharging paths.