A die separation ring that causes non-uniform expansion of a semiconductor wafer during a semiconductor wafer expansion process. The die separation ring includes an annular body that extends about a central axis. The annular body of the die separation ring includes a first portion having a first elevation and a second portion having a second elevation that is lower than the first elevation. A third portion extends between the first portion and the second portion forming a transition between the first portion and the second portion.

Techniques are described for the use of moats for isolating and singulating semiconductor devices formed on a wafer. Described techniques use dielectric films, such as an oxide-nitride film, to coat moat surfaces and provide passivation. The dielectric films may form a junction with a metal contact layer, to reduce electrical overstress that may otherwise occur in the resulting semiconductor devices. To ensure coverage of the moat surfaces, spray coating of a positive photoresist may be used.

Implementations of a method of singulating silicon carbide may include in a plurality of X-direction die streets, irradiating with a laser beam focused at a focal point a first depth into the thickness in a predetermined number of X-passes to form a first modified region and a second modified region. The method may also in include irradiating in a Y-direction with the laser beam focused a focal point a second depth into the thickness in a predetermined number of Y-passes to form a first modified region and a second modified region. The method may include breaking first in the Y-direction and then in the X-direction along the plurality of X-direction die streets and the plurality of Y-direction die streets, respectively, using an anvil. The method also may include expanding a tape to separate a plurality of die from the silicon carbide substrate.

A laser processing device includes: a light source configured to output laser light; a space light modulator for modulating the laser light output from the light source in accordance with a modulation pattern and outputting the modulated laser light; a converging lens for converging the laser light output from the space light modulator to an object, and forming a converging spot on the object; a movement unit for relatively moving the converging spot with respect to the object; and a control unit for relatively moving, while setting a position of the converging spot in a Z direction intersecting with an incident surface of the laser light on the object at a first Z position, the converging spot along a line extended in an X direction along the incident surface by controlling at least the space light modulator and the movement unit.

A semiconductor package includes a microelectronic die with an electrically conductive substrate that has an isolation dielectric layer on a back surface of the substrate. The isolation dielectric layer extends onto perimeter sidewalls of the substrate. The isolation dielectric layer on the back surface is attached to an electrically conductive member of a lead frame. The isolation dielectric layer isolates the substrate from the electrically conductive member. The microelectronic die is formed by forming isolation kerfs in the substrate, extending from the back surface. Sides of the isolation kerfs form perimeter sidewalls of the substrate. The isolation dielectric layer is formed on the back surface and in the isolation kerfs. The microelectronic die is singulated through the isolation kerfs. The isolation dielectric layer remains on the back surface and the perimeter sidewalls.

Power semiconductor devices and power semiconductor device packages are provided. In one example, a power semiconductor device package includes a submount and a semiconductor die on the submount. In some examples, the semiconductor die includes a metallization structure, a first passivation layer on the metallization structure, a buffer layer on the first passivation layer, a second passivation layer on the buffer layer, and a polyimide layer directly on the second passivation layer. In some examples, the second passivation layer includes the same material as the first passivation layer.

A method for manufacturing a semiconductor device includes a step of preparing a semiconductor substrate that has a first main surface on one side and a second main surface on the other side, the semiconductor substrate on which a plurality of device forming regions and an intended cutting line that demarcates the plurality of device forming regions are set, a step of forming a first electrode that covers the first main surface in each of the device forming regions, a step of forming a second electrode that covers the second main surface, a step of partially removing the second electrode along the intended cutting line such that the semiconductor substrate is exposed, and forming a removed portion that extends along the intended cutting line, and a step of cutting the semiconductor substrate along the removed portion.

A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 m or less.

In a manufacturing method of a semiconductor device, a wafer in which multiple semiconductor elements is formed and having a first surface and a second surface opposite to each other is prepared, and a groove is formed on the first surface of the wafer along a boundary between adjacent semiconductor elements in the multiple semiconductor elements. The wafer is attached to a support plate in such a manner that the first surface of the wafer faces the support plate, and a scribing blade is pressed against the second surface of the wafer along the boundary to form a vertical crack inside the wafer along the boundary. Then, a breaking blade is pressed against the wafer along the boundary to cleave the wafer along the boundary.

A Low Pressure Chemical Vapor Deposition (LPCVD) technique is provided to produce improved dielectric/semiconductor interfaces for GaN-based electronic devices. Using the LPCVD technique, superior interfaces are achieved through the use of elevated deposition temperatures (>700 C.), the use of ammonia to stabilize and clean the GaN surface, and chlorine-containing precursors where reactions with chlorine remove unwanted impurities from the dielectric film and its interface with GaN. The LPCVD silicon nitride films have less hydrogen contamination, higher density, lower buffered-HF etch rates, and lower pin hole density than films produced by other deposition techniques making the LPCVD coatings suitable for device passivation. A metal insulator semiconductor (MIS) structures fabricated with LPCVD SiN on GaN exhibit near ideal capacitance-voltage behavior with both charge accumulation, depletion, and inversion regimes.