A design engine automates portions of a mechanical assembly design process. The design engine generates a user interface that exposes tools for capturing input data related to the design problem. Based on the input data, the design engine performs various operations to generate a formalized problem definition that can be processed by a goal-driven optimization algorithm. The goal-driven optimization algorithm generates a spectrum of potential design options. Each design option describes a mechanical assembly representing a potential solution to the design problem.

Disclosed are example embodiments of methods and systems for identifying and quantifying manufacturing defects of a manufactured dental prosthesis. Certain embodiments of the system for performing quality control on manufactured dental prostheses includes: a quality control module configured to determine whether the dental prosthesis is a good or a defective product based at least on a differences model generated by comparing a design model and a scanned model of the manufactured dental prosthesis.

A method for fabricating a component of an abatement apparatus is disclosed. The method comprises: meshing a 3D model representation of a component defining a reaction chamber of an abatement apparatus based on specified component characteristics to define an optimised finite element representation of the component; and fabricating the optimised finite element representation. In this way, a 3D model of a component of an abatement apparatus can be generated from which its performance can be modelled. Particular characteristics of the component may be defined which affect the operation of the abatement apparatus. Those characteristics may then be used to generate the optimized finite element representation of the component which has those characteristics using meshing (it will be appreciated that meshing is the operation of representing a geometric object as a set of finite elements). The optimized finite element representation may then fabricated, reliably producing a component having the required characteristics.

A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.

A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Provided is a method of manufacturing a semiconductor device. the method comprises receiving layout data including a plurality of pieces of pattern data, the plurality of pieces of pattern data having through first to N.sup.th unique patterns (N is a natural number greater than or equal to two), calculating first to N.sup.th density values of the first to N.sup.th unique patterns from the layout data and calculating first to N.sup.th populations of the first to N.sup.th unique patterns from the layout data, performing sampling by selecting some unique patterns among the first to N.sup.th unique patterns, the selecting based on the first to N.sup.th density values and the first to N.sup.th populations, and performing etch modeling on sampled patterns of the plurality of pieces of pattern data, the sampled patterns corresponding to the selected unique patterns.

Embodiments of the present disclosure relate to parallel mask rule checking on evolving mask shapes in optical proximity correction (OPC) flows for integrated circuit designs. Systems and methods are disclosed that perform mask (manufacturing) rule checks (MRC) in parallel, sharing information to maintain symmetry when violations are corrected. In an embodiment the shared information is also used to minimize changes to the geometric area of proposed mask shapes resulting from the OPC. In contrast to conventional systems, MRC is performed for multiple edges in parallel, sharing information between the different edges to encourage symmetry. In an embodiment, all edges may be adjusted in parallel to reduce mask-edge traversal bias.

A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Systems and methods for predicting locations of overheating of one or more objects for build of the one or more objects by additive manufacturing using simulation. A method includes simulating temperature of an object as a function of spatial location during a layer by layer build using powder based additive manufacturing comprising determining a temperature over time at a plurality of locations of a plurality of layers of the object. The method further includes calculating, for each of the plurality of locations, an overheating index that is a function of each of a corresponding maximum temperature, thermal gradient, and heat modulus. The method further includes, based on one or more overheating indexes of one or more locations exceeding the threshold indicating overheating, adjusting a build of the object.