Methods, apparatuses, and systems related to an over-sculpted storage node are described. An example method includes forming an opening in a pattern of materials. The method further includes performing an etch to over-sculpt the opening. The method further includes depositing a storage node material in the over-sculpted opening to form an over-sculpted storage node. The method further includes performing an etch to remove portions of the pattern of materials. The method further includes performing an etch on the storage node material to trim the over-sculpted storage node.

Disclosed herein are IC structures with capacitors with porous materials. In one aspect, an IC structure may include a capacitor having first and second electrodes, and an insulator therebetween, wherein the first electrode includes a porous semiconductor material with dopants. In another aspect, an IC structure may include a capacitor having first and second electrodes, and an insulator therebetween, wherein the insulator includes a porous semiconductor material with oxygen.

A semiconductor device includes a substrate having a recess region, a first electrode in the recess region and having a three-dimensional network structure, a first dielectric layer in the recess region and covering the first electrode, a second electrode in the recess region and covering the first dielectric layer, and a molding layer filling a remaining portion of the recess region and covering the second electrode.

Electrodes for a capacitor having nanotextured surfaces is disclosed. The nanotextured surfaces comprise nanograins of the metal and are fabricated by oxidizing and reducing a metal in the electrodes. The nanotextured surfaces significantly increase surface areas of the electrodes, as such improves a capacitance of the capacitor. The fabrication method can produce stacked capacitors with horizontally oriented electrodes or vertically oriented electrodes. The fabrication method may be of low cost and may produce high performance capacitors.

A method of forming a semiconductor device includes forming a first electrode on a single-crystal structure. A dielectric layer is formed on the first electrode. A second electrode is formed on the dielectric layer. The forming a dielectric layer includes forming a first dielectric layer having a single-crystal perovskite structure on the first electrode, and forming a second dielectric layer on the first dielectric layer. An upper surface of the first dielectric layer adjacent to the second dielectric layer has a greater surface roughness than an upper surface of the second dielectric layer adjacent to the second electrode.

To provide a thin film capacitor having high adhesion performance with respect to a circuit substrate. A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil. The first and second electrode layers are formed in an area surrounded by an outer peripheral area of the upper surface of the metal foil so as not to cover the outer peripheral area. The outer peripheral area of the roughened upper surface of the metal foil is thus exposed, so that adhesion performance with respect to a circuit substrate can be enhanced.

A capacitor includes a silicon substrate, a dielectric layer, and a conductor layer. The silicon substrate has a doped layer. The doped layer includes a first doped layer disposed along a second region of a first principal surface of the silicon substrate, a second doped layer disposed at a bottom part of the porous part of the silicon substrate, and a third doped layer disposed at a side part of the porous part of the silicon substrate. The doped layer includes a first portion connecting the first doped layer to the third doped layer and having a first curved part concavely curved in a cross-sectional view. The doped layer includes a second portion connecting the second doped layer to the third doped layer and having a second curved part convexly curved in the cross-sectional view.

Provided is a semiconductor device including a buffer die configured to communicate with an external device, a memory die stack including a plurality of memory dies stacked on the buffer die and connected to the buffer die through a plurality of through silicon vias, and a capacitor arranged on an upper portion of an uppermost memory die among the plurality of memory dies, wherein the capacitor surrounds at least some surfaces of the plurality of memory dies, when viewed in a top down view.