An electrostatic discharge semiconductor device and a manufacturing method thereof are disclosed. The electrostatic discharge semiconductor device includes: a substrate, an epitaxial layer and a first well region; a second well region and a third well region located on sides of the first well region respectively; a fourth well region extending in the first well region; fifth and sixth well regions on sides of the fourth well region; a first injection region and a second injection region. The second injection region in the second well region and third well region, and the first injection region in the fifth well region and sixth well region are connected to a cathode, and all injection regions in the fourth well region are connected to an anode, to form a lateral triode current discharge path, which increases the holding voltage and adjusts the avalanche breakdown voltage and trigger voltage, and enhances electrostatic protection capability.

An integrated circuit includes a semiconductor substrate, first and second doping regions in the substrate, a first insulating layer on a first surface of the semiconductor substrate, the first insulating layer having first and second openings above the first and second doping regions, a polysilicon layer on the first insulating layer, the polysilicon layer having first and second openings above the first and second openings of the first insulating layer, a second insulating layer on the polysilicon layer and having first and second openings above the first and second openings of the polysilicon layer, a first contact element disposed in the first openings, a second contact element disposed in the second openings, the first and second contact elements being in contact with the first and second doping regions.

Bipolar junction devices, and methods for manufacturing the same. At least one example of making a bipolar junction device includes doping an upper side of a substrate with an upper P-type region and an upper N-type region, thermally diffusing the upper P-type region and the upper N-type region, the substrate having a thickness of greater than 150 microns during the thermally diffusing, reducing the thickness of the substrate to between and including 40 and 150 microns, doping a lower side of the substrate with a lower P-type region and a lower N-type region, and then localized-heat annealing the lower P-type region and the lower N-type region.

A method of manufacturing a semiconductor device having a combination structure of a horizontal oxide layer structure and a vertical oxide layer structure, can include: etching from an upper surface of the semiconductor substrate to inside of the semiconductor substrate to form a trench; depositing oxides in the trench to form the vertical oxide layer structure; etching the vertical oxide layer structure from an upper surface thereof to decrease height of the vertical oxide layer structure, and to make a top surface of the vertical oxide layer structure be below the upper surface of the semiconductor substrate, in order to expose side surfaces of the trench; and forming, by an oxidation process, the horizontal oxide layer structure to cover part of the upper surface of the semiconductor substrate and the upper surface of the vertical oxide layer structure.

A semiconductor device includes a substrate; a fin structure disposed over the substrate; a gate structure disposed over the substrate, wherein an extension direction of the fin structure intersects an extension direction of the gate structure; and a first well disposed under the gate structure, corresponding to an emitter region of the semiconductor device, and having a first conductivity type, wherein the first well is adjacent to a well block layer, and the well block layer is disposed under the gate structure in the emitter region; wherein the well block layer has a first doping concentration of a well implant, the first well has a second doping concentration of the well implant, and the first doping concentration is less than the second doping concentration.

A bipolar junction transistor includes an emitter region, a base region, a collector region and a plurality of fin structures. The emitter region is disposed on a substrate. The base region surrounds the emitter region. The collector region surrounds the base region. The plurality of fin structures are disposed in the base region and surround the emitter region, and the plurality of fin structures fixedly extend along a direction and parallel to each other.

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate having an upper substrate surface, an active well region, a first terminal well region, and a second terminal well region. The active well region is in the substrate, and the first terminal well region and the second terminal well region are in the active well region. The second terminal well region is spaced apart from the first terminal well region. The first terminal well region and the second terminal well region each includes a first doped region, a first contact region having at least a portion in the first doped region, and a second contact region spaced apart from the first doped region.

A semiconductor device includes a semiconductor substrate, a base region, an emitter region, a collector region, and an element isolation insulating film. The semiconductor substrate has a main surface. The base region has a first conductivity type and is disposed in a surface layer of the semiconductor substrate that is close to the main surface. The emitter region has a second conductivity type and is disposed in a surface layer of the base region. The collector region has the second conductivity type and is disposed at a portion in the surface layer of the semiconductor substrate apart from the emitter region. The element isolation insulating film is disposed on the main surface, and has a thermal oxide film being in contact with a junction interface between the base region and the emitter region.

A lateral bipolar transistor includes an emitter region doped with a first conductivity type, having a first width and a first average doping concentration; a collector region doped with the first conductivity type, having a second width greater than the first width of the emitter region and a second average doping concentration lower than the first average doping concentration; and a base region positioned between the emitter and collector regions. The emitter, collector and base regions are arranged in a silicon layer on an insulator layer on a substrate. A substrate region that is deprived of the silicon and insulator layers is positioned on a side of the collector region. A bias circuit is coupled, and configured to deliver, to the substrate region a bias voltage. This bias voltage is controlled to modulate an electrostatic doping of the collector region.

A semiconductor device includes a guardring including a first doped region and a first contact over the first doped region, a base including a second doped region and a second contact over the second doped region, a collector including a third doped region and a third contact over the third doped region, and an emitter including a fourth doped region and a fourth contact over the fourth doped region. The emitter, the collector, the base, and the guardring are separated on a backside of the semiconductor device via shallow trench isolation (STI) or floating gates.