Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes: a substrate: a drain region vertically disposed on the substrate; a body region vertically disposed on the drain region; a source region vertically disposed on the body region; a bit-line connected to the drain region and extending in a first direction; and a word-line connected to the source region and extending in a second direction that is different from the first direction. The drain region, the body region, and the source region together define a pillar extending in a third direction that is perpendicular to the first and second direction.

An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

An alternating stack of insulating layers including a silicon oxide material and electrically conductive layers is formed over a substrate. Sidewalls of the insulating layers are selectively silylated with a chemical including at least one silyl group without silylating sidewalls of the electrically conductive layers. Silicon-containing barrier material portions are formed by selectively growing a first silicon-containing barrier material from surfaces of the electrically conductive layers without growing the first silicon-containing barrier material from silylated surfaces of the insulating layers. A memory material layer is formed on the silicon-containing barrier material portions and the sidewalls of the insulating layers. A vertical conductive line is formed on the memory material layer.

An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.

Memory devices based on tungsten oxide memory elements are described, along with methods for manufacturing such devices. A memory device includes a plug extending upwardly from a top surface of a substrate through a dielectric layer; a bottom electrode having tungsten on an outside surface, the bottom electrode extending upwardly from a top surface of the plug; an insulating material in contact with the tungsten on the outside surface of, and surrounding, the bottom electrode; a memory element on an upper surface of the bottom electrode, the memory element comprising a tungsten oxide compound and programmable to at least two resistance states; and a top electrode overlying and contacting the memory element. The plug has a first lateral dimension, and the bottom electrode has a lateral dimension parallel with the first lateral dimension of the plug that is less than the first lateral dimension.

Apparatus and methods for reducing minority carriers in a memory array are described herein. Minority carriers diffuse between ON cells and OFF cells, causing disturbances during write operation as well as reducing the retention lifetime of the cells. Minority Carrier Lifetime Killer (MCLK) region architectures are described for vertical thyristor memory arrays with insulation trenches. These MCLK regions encourage recombination of minority carriers. In particular, MCLK regions formed by conductors embedded along the cathode line of a thyristor array, as well as dopant MCLK regions are described, as well as methods for manufacturing thyristor memory cells with MCLK regions.