A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

Disclosed in the present disclosure is a topological structure for an IP core. The topological structure comprises a first topological structure and a second topological structure, wherein the first topological structure comprises a drive chip, multi-level first signal lines and at least two first loads, a signal output of a previous-level first signal line being connected to signal input of two next-level first signal lines which are connected in parallel, a signal input of a first-level first signal line being connected to a signal output of the drive chip, and an output of each last-level first signal line being connected to a first load; and the second topological structure comprises a plurality of branch structures, each of which comprises at least one second load, a signal input of each branch structure being connected to a signal output of a last-level first signal line of the first topological structure.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.