A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

Techniques are described for forming a sealed cavity within a semiconductor wafer, where a conductor wafer includes a structure, such as a T-gate electrode or passive component, formed over a substrate. The sealed-cavity structure may be embedded into the wafer without interfering with any subsequent processes. That is, once the cavity is closed, any subsequent backend processes may continue as usual.

A semiconductor device includes: a semiconductor layer, a gate insulating layer, and a gate electrode sequentially formed in a trench formed to a predetermined depth from a first surface of a first substrate; a third substrate bonded to a second surface opposite to the first surface of the first substrate; and an air gap interposed between the semiconductor layer and the first substrate and between the semiconductor layer and the third substrate.

A new semiconductor structure is disclosed. The semiconductor structure includes patterned dielectric layers disposed between the field plates and the channel layer. These patterned dielectric layers serve to further shape the electric field in the channel layer. This structure is not only applicable to III-nitride semiconductor devices, such as transistors, diodes or any other devices, but also is applicable to other semiconductor devices, such as Si LDMOS, SiC transistors, GaAs transistors.

A semiconductor device includes: a semiconductor layer, a gate insulating layer, and a gate electrode sequentially formed in a trench formed to a predetermined depth from a first surface of a first substrate; a third substrate bonded to a second surface opposite to the first surface of the first substrate; and an air gap interposed between the semiconductor layer and the first substrate and between the semiconductor layer and the third substrate.

A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a base substrate including a trench, where the trench includes a gate structure whose top surface is lower than a top surface of the trench; first etch stop layers, where the first etch stop layers cover the top surface of the gate structure, part of a side wall of the trench, and an upper surface of the base substrate; an enclosed isolation structure positioned between the first etch stop layers in the trench, where the enclosed isolation structure at least plugs an opening of the trench; and an air gap positioned between the first etch stop layer and the enclosed isolation structure, where the air gap at least includes a transverse portion, and a bottom of the enclosed isolation structure is positioned on the transverse portion.

A semiconductor device includes an island-shaped semiconductor including a first portion and a second portion that is provided integrally alongside the first portion in a first direction and has a width in a direction identical to a width of the first portion along a second direction intersecting the first direction larger than the width of the first portion, the first portion and the second portion each including an upper surface and a side surface, an insulating layer that surrounds each of the first portion and the second portion, a field effect transistor including a gate electrode that is separated from the second portion and is provided across the upper surface and the side surface of the first portion with a gate insulating film interposed therebetween, and a dielectric portion that is provided between the gate electrode and the second portion and is lower in relative permittivity than the insulating layer.

A semiconductor device according to an embodiment includes a first electrode, a second electrode, and a semiconductor layer. The semiconductor layer includes a first conductivity type first semiconductor region, and a second conductivity type second semiconductor region disposed on the first semiconductor region. The semiconductor device further includes: an insulating region having a cavity extending from an upper end in the first direction; a first control electrode disposed in the insulating region so as to face the second semiconductor region in a second direction ; a second control electrode disposed in the insulating region so as to face the first control electrode in the second direction with the cavity interposed between the first control electrode and the second control electrode; and a conductive portion electrically connected to the first electrode, disposed in the insulating region, and having an upper surface at least partially exposed to a bottom of the cavity.

A semiconductor memory device includes a gate array including a plurality of conductive layers alternately stacked with a plurality of interlayer insulating structures in a stack direction, a cell pillar extending through the gate array in the stack direction, and a porous layer surrounding the cell pillar, wherein an opening or an air gap is formed between a first section of a first interlayer insulating structure of the plurality of interlayer insulating structures and a second section of the first interlayer insulating structure, the opening surrounding the porous layer disposed between the first section and the second section.