A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, and a dielectric layer. The MOS transistor includes a gate structure formed over the substrate. The dielectric layer is formed aside the gate structure, and the dielectric layer is doped with a strain modulator. An effective lattice constant of the dielectric layer modified by the doping with the strain modulator is different from an effective lattice constant of the dielectric layer prior to the doping.

Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n.sup. drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n.sup. drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.

Hydrogen atoms and crystal defects are introduced into an n semiconductor substrate by proton implantation. The crystal defects are generated in the n semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.

An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating film formed over a semiconductor substrate. At that time, a mask layer for formation of the opening is formed over the insulating film. The insulating film is dry etched and then wet etched. The dry etching step is finished before the semiconductor substrate is exposed at the bottom of the opening, and the wet etching step is finished after the semiconductor substrate is exposed at the bottom of the opening.

A method for fabricating a semiconductor device is disclosed. A plurality of trenches is formed at a predetermined cell pitch in an upper surface portion of a substrate. A first insulation film is formed on the substrate. A gate electrode is formed and partially filled within each trench. A first conductivity type region is formed in the upper surface portion of the substrate between the trenches. A second conductivity type region is formed in a side surface of the substrate between the trenches and the first conductivity type region. A second insulation film is formed covering the gate electrode within each trench, wherein an upper surface of the second insulation film is positioned lower than an upper surface of the substrate. A source metal layer is formed on the second insulation film and electrically connected to the first conductivity type region and the second conductivity type region.

Techniques herein provide a chamber and substrate cleaning solution for etching and removing byproducts between separate etching steps. Such techniques include using a cleaning step based on fluorine chemistry, which is executed in between separate etch steps or divided etch steps. Such a technique can be executed in situ for improved efficiency. Other benefits include increasing etching depth/aspect ratios, and preventing post-etching defects including physical contact with neighboring gates, etc. Techniques herein are especially beneficial when applied to relatively small feature openings.

Provided are a power device having an improved field stop layer and a method of manufacturing the same. The method can include performing a first ion implant process by implanting impurity ions of a first conductive type into a front surface of a semiconductor substrate to form an implanted field stop layer where the semiconductor substrate is the first conductive type. The method can include performing a second ion implant process by implanting impurity ions of the first conductive type into a first part of the implanted field stop layer such that an impurity concentration of the first part of the implanted field stop layer is higher than an impurity concentration of a second part of the implanted field stop layer.

A method for manufacturing a bipolar junction transistor is provided. A layer stack is provided that comprises a semiconductor substrate having a trench isolation; an isolation layer arranged on the semiconductor substrate, wherein the first isolation layer comprises a recess forming an emitter window; lateral spacers arranged on sidewalls of the emitter window; a base layer arranged in the emitter window on the semiconductor substrate; and an emitter layer arranged on the isolation layer, the lateral spacers and the base layer. A sacrificial layer is provided on the emitter layer thereby overfilling a recess formed by the emitter layer due to the emitter window. The sacrificial layer is selectively removed up to the emitter layer while maintaining a part of the sacrificial layer filling the recess of the emitter layer. The emitter layer is selectively removed up to the isolation layer while maintaining the filled recess of the emitter layer.