An image processing apparatus includes processing circuitry. The processing circuitry is configured to detect a positional shift amount of each of a plurality of images; select a composite target image from the plurality of images based on the detected positional shift amount; and obtain a composite image based on the positional shift amount and the selected composite target image.

An image sensor according to one embodiment may comprise: an image sensing unit which receives light and generates a first Bayer pattern having a first resolution; and a processor which receives a second Bayer pattern that is at least a portion of the first Bayer pattern from the image sensing unit, and then generates a third Bayer pattern having a higher resolution than the second alignment unit on the basis of the received second Bayer pattern.

An image sensor operating in multiple resolution modes including a low resolution mode and a high resolution mode includes a pixel array including a plurality of pixels, wherein each pixel in the plurality of pixels comprises a micro-lens, a first subpixel including a first photodiode, a second subpixel including a second photodiode, and the first subpixel and the second subpixel are adjacently disposed and share a floating diffusion region. The image sensor also includes a row driver providing control signals to the pixel array to control performing of an auto focus (AF) function, such that performing the AF function includes performing the AF function according to pixel units in the high resolution mode and performing the AF function according to pixel group units in the low resolution mode. A resolution corresponding to the low resolution mode is equal to or less than ¼ times a resolution corresponding to the high resolution mode.

An image processing device includes an interface and a control circuit. The interface is configured to receive input line signals in synchronization with input horizontal synchronization signals, respectively. The control circuit is configured to store line image data contained in each of input line signals in the order of reception, generate internal horizontal synchronization signals, and output internal line signals containing the line image data in the input line signals, in synchronization with the internal horizontal synchronization signals, respectively. The input line signals include a first input line signal containing first line image data, and the internal line signals include a first internal line signal containing the first line image data. A horizontal cycle of the internal horizontal synchronization signal corresponding to the first internal line signal is less than a horizontal cycle of the input horizontal synchronization signal corresponding to the first input line signal.

An image processing apparatus includes at least one processor or circuit configured to execute a plurality of tasks including an image acquiring task configured to acquire a first image and a second image that have been obtained by imaging at imaging positions different from each other, an image restoration processing task configured to acquire a first restored image and a second restored image by performing image restoration processing for the first image and the second image respectively, and a pixel increasing processing task configured to acquire a pixel increased image using the first restored image and the second restored image.

Provided is an imaging device that performs a pixel shift for moving an imaging element a predetermined shift amount for each exposure to acquire a plurality of images and synthesizes the plurality of images to generate a high-resolution image, the imaging device including: a signal processing unit that sets an image blur correction target value on the basis of a shake of the imaging device detected by a vibration detection unit; and an image blur correction unit that corrects an image blur in accordance with the image blur correction target value, wherein the signal processing unit fixes the image blur correction target value to a predetermined value when the pixel shift is performed.

An image processing device includes an interface and a control circuit. The interface is configured to receive input line signals in synchronization with input horizontal synchronization signals, respectively. The control circuit is configured to store line image data contained in each of input line signals in the order of reception, generate internal horizontal synchronization signals, and output internal line signals containing the line image data in the input line signals, in synchronization with the internal horizontal synchronization signals, respectively. The input line signals include a first input line signal containing first line image data, and the internal line signals include a first internal line signal containing the first line image data. A horizontal cycle of the internal horizontal synchronization signal corresponding to the first internal line signal is less than a horizontal cycle of the input horizontal synchronization signal corresponding to the first input line signal.

An image processing device includes one or more processors configured to: generate a high-resolution combined image by aligning the plurality of images with each other in a high-resolution image space based on an amount of displacement between the plurality of images, and combining the plurality of images; generate at least two low-resolution combined images by generating at least two groups each composed of at least two images by dividing the plurality of images in the time direction, aligning the at least two images in each of the groups with each other in a low-resolution image space based on the amount of displacement, and combining the at least two images through weighted addition; calculate, in each region, a feature quantity pertaining to a correlation between the generated at least two low-resolution combined images; and correct the high-resolution combined image based on the calculated feature quantity.

A solid-state imaging element that detects address events captures high-quality images. The solid-state imaging element includes a pixel array section that has a plurality of pixels including a specific pixel arranged in a two-dimensional lattice pattern. The specific pixel includes a pixel circuit and two analog-digital converters. The pixel circuit outputs two analog signals proportional to an amount of charge produced by photoelectric conversion. The analog-digital converters convert the respective two analog signals into digital signals with different resolutions.

An image shift amount calculation apparatus comprises: an obtaining unit that obtains a pair of images having parallax; a generation unit that generates, from the pair of images, an image pair for each of a plurality of hierarchal levels having different resolutions; and a calculation unit calculates an image shift amount for an image pair in a predetermined first hierarchal level among the plurality of hierarchal levels, determines, on the basis of the image shift amount in the first hierarchal level, a second hierarchal level, among the plurality of hierarchal levels, where the calculation of the image shift amount is to end, and calculates an image shift amount of the image pair in the second hierarchal level using the image shift amount in the first hierarchal level.