A semiconductor device having a channel formed from a nanowire with a multi-dimensional diameter is provided. The semiconductor device comprises a drain region formed on a semiconductor substrate. The semiconductor device further comprises a nanowire structure formed between a source region and the drain region. The nanowire structure has a first diameter section joined with a second diameter section. The first diameter section is coupled to the drain region and has a diameter greater than the diameter of the second diameter section. The second diameter section is coupled to the source region. The semiconductor device further comprises a gate region formed around the junction at which the first diameter section and the second diameter section are joined.

Methods of semiconductor arrangement formation are provided. A method of forming the semiconductor arrangement includes forming a first nucleus on a substrate in a trench or between dielectric pillars on the substrate. Forming the first nucleus includes applying a first source material beam at a first angle relative to a top surface of the substrate and concurrently applying a second source material beam at a second angle relative to the top surface of the substrate. A first semiconductor column is formed from the first nucleus by rotating the substrate while applying the first source material beam and the second source material beam. Forming the first semiconductor column in the trench or between the dielectric pillars using the first source material beam and the second source material beam restricts the formation of the first semiconductor column to a single direction.

A method for transferring at least one thin film from a first substrate to a second substrate is provided, the thin film having a first side and an opposing second side and the second side of the thin film being arranged on a first side of the first substrate, at least part of the first substrate being subsequently removed and the second substrate being brought into contact, via its first side, with the second side of the thin film, wherein a liquid is supplied to the contact surface and then at least some of the liquid is removed by rotating the thin film and the second substrate.

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

A method, for manufacturing a silicon carbide semiconductor device, includes: forming a silicon carbide epitaxial film on a silicon carbide substrate; flattening a surface of the epitaxial film by using chemical mechanical polishing such that the surface of the epitaxial film has an arithmetic mean roughness Ra of 0.3 nm or less; thermally oxidizing the surface of the epitaxial film to form a sacrificial oxide; removing the sacrificial oxide; and cleaning, by using deionized water, a surface of the epitaxial film exposed by the removing of the sacrificial oxide.

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

A process for producing a light emitting diode device, the process including: forming a plurality of quantum dots on a surface of a layer including a first area and a second area, the forming including: exposing the first area of the surface to light having a first wavelength while exposing the first area to a quantum dot forming environment that causes the quantum dots in the first area to form at a first growth rate while the quantum dots have a dimension less than a first threshold dimension; exposing the second area of the surface to light having a second wavelength while exposing the second area to the quantum dot forming environment that causes the quantum dots in the second area to form at a third growth rate while the quantum dots have a dimension less than a second threshold dimension; and processing the layer to form the LED device.

An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

Method and devices are disclosed for device manufacture of gallium nitride devices by growing a gallium nitride layer on a silicon substrate using Atomic Layer Deposition (ALD) followed by rapid thermal annealing. Gallium nitride is grown directly on silicon or on a barrier layer of aluminum nitride grown on the silicon substrate. One or both layers are thermally processed by rapid thermal annealing. Preferably the ALD process use a reaction temperature below 550 C. and preferable below 350 C. The rapid thermal annealing step raises the temperature of the coating surface to a temperature ranging from 550 to 1500 C. for less than 12 msec.