Methods for depositing an amorphous silicon layer on wafers are disclosed. A process wafer, a control wafer, and a dummy wafer may be loaded into a chamber where an amorphous silicon layer may be deposited on the process wafer. Afterwards, the process wafer and the control wafer may be removed from the chamber. The chamber and the dummy wafers are dry cleaned together. The dry cleaned dummy wafers are used in the next run for depositing amorphous silicon layer. The process may be controlled by a computer system issuing a control job comprising a first process job and a second process job, wherein the first process job is to deposit an amorphous silicon layer on the process wafer, and the second process job is to dry clean the chamber and the dummy wafer.

A step of preparing a silicon carbide substrate (S11), a step of forming a first silicon carbide semiconductor layer on the silicon carbide substrate using a first source material gas (S12), and a step of forming a second silicon carbide semiconductor layer on the first silicon carbide semiconductor layer using a second source material gas (S13) are provided. In the step of forming a first silicon carbide semiconductor layer (S12) and the step of forming a second silicon carbide semiconductor layer (S13), ammonia gas is used as a dopant gas, and the first source material gas has a C/Si ratio of not less than 1.6 and not more than 2.2, the C/Si ratio being the number of carbon atoms to the number of silicon atoms.

Layered oxide structures comprising an overlayer of high quality VO.sub.2 and methods of fabricating the layered oxide structures are provided. Also provided are high-speed switches comprising the layered structures and methods of operating the high-speed switches. The layered oxide structures include high quality VO.sub.2 epitaxial films on isostructural SnO.sub.2 growth templates.

Fabricating a semiconductor structure including forming a nanocrystalline core from a first semiconductor material, forming a nanocrystalline shell from a second, different, semiconductor material that at least partially surrounds the nanocrystalline core, wherein the nanocrystalline core and the nanocrystalline shell form a quantum dot. Fabrication further involves forming an insulator layer encapsulating the quantum dot to create a coated quantum dot, and forming an additional insulator layer on the coated quantum.

A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.

In a method of manufacturing a quantum dot, a core may be formed using (utilizing) at least one cation precursor and at least one anion precursor. The core may be reacted with a shell forming precursor and a ligand forming precursor for more than one hour to form a shell enclosing the core and a ligand. A nanoparticle including the core, the shell and the ligand may be washed.

A method for preparing an LTPS membrane, including: forming an amorphous silicon (a-Si) layer (S3) on a substrate (S1) by a patterning process, in which the a-Si layer (S3) comprises a plurality of convex structures (S32) and etched areas (S31) which are disposed along circumference of the plurality of convex structures and partially etched; and performing excimer laser crystallization (ELC) on the a-Si layer (S3) and obtaining the LTPS membrane. A thin-film transistor (TFT) and a display device are further disclosed, which are used for overcoming poor uniformity of the polysilicon membrane prepared by the ELC technology.

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

A method heteroepitaxially deposits a silicon germanium layer on a substrate. The silicon germanium layer has a composition Si.sub.1-xGe.sub.x, where 0.01x1. The substrate is a silicon single crystal wafer or a silicon-on-insulator wafer. The method includes: providing a mask layer atop the substrate; removing the mask layer in an edge region of the substrate to provide access to an annular-shaped free surface of the substrate in the edge region of the substrate surrounding a remainder of the mask layer; depositing an edge reservoir consisting of a relaxed or partially relaxed silicon germanium layer atop the annular-shaped free surface of the substrate; removing the remainder of the mask layer; and depositing the silicon germanium layer atop the substrate and atop the edge reservoir, the silicon germanium layer contacting an inner lateral surface of the edge reservoir.