An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

In some embodiments, a method includes providing an input voltage to a level-shifting circuit, where the input voltage is in a first power domain, shifting the input voltage to an output voltage using the level-shifting circuit, where the output voltage is in a second power domain different from the first power domain, and where the level-shifting circuit is coupled to power supply voltages in the second power domain. The method further includes in response to an electrostatic discharge (ESD) event, turning off a first transistor coupled between a first node of the level-shifting circuit and a reference low voltage level of the second power domain.

Disclosed is an integrated protecting circuit, which detects ESD and EOS pulses to prevent an over-voltage from being applied to a semiconductor device. The integrated protecting circuit includes a first detector configured to detect an occurrence of an electrical over-stress between a first node to which a first voltage is applied and a second node to which a second voltage is applied, a second detector configured to detect an occurrence of an electrostatic discharge between the first and second nodes, a determination circuit configured to receive separate outputs of the first and second detectors at the same time and to generate a control signal, and a clamping device configured to perform a turn on/off operation in response to the control signal such that a voltage between the first and second nodes is clamped into a constant voltage.

Apparatus and methods for providing transient overstress protection with active feedback are disclosed. In certain configurations, a protection circuit includes a transient detection circuit, a bias circuit, a clamp circuit, and a sense feedback circuit that generates a positive feedback current when the clamp circuit is clamping. The transient detection circuit can detect a presence of a transient overstress event, and can generate a detection current in response to detection of the transient overstress event. The detection current and the positive feedback current can be combined to generate a combined current, and the bias circuit can turn on the clamp circuit in response to the combined current. While the transient overstress event is present and the clamp circuit is clamping, the sense feedback circuit can generate the positive feedback current to maintain the clamp circuit turned on for the event's duration.

An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

According to an embodiment, an electrostatic discharge (ESD) protection circuit includes a first transistor having a first source/drain coupled to a first input/output terminal, a second source/drain coupled to a first reference voltage terminal, and a gate coupled to a second reference voltage terminal. The ESD protection circuit further includes a direct current (DC) blocking circuit having a first input/output node coupled to the first input/output terminal, a second input/output node configured to be coupled to a useful circuit, and a third input/output node coupled a gate of the first transistor.

This static electricity protection circuit starts a discharge operation only if an applied voltage is greater than or equal to a set voltage, and protects a discharge circuit also when noise or the like is applied during a normal operation. This static electricity protection circuit includes: a resistor R1 and clamp circuit that are connected in series between nodes N1 and N2; a first transistor that turns on in accordance with an increase in a potential difference generated in the resistor R1; a resistor R2 and capacitor C2 that are connected via a node N4 between the nodes N1 and N2; a second transistor that is connected in series with the first transistor between the nodes N1 and N5; a resistor R3 connected between the nodes N5 and N2; a third transistor connected between the nodes N4 and N2; and a discharge circuit connected between the nodes N1 and N2.

The present overcurrent protective device comprises an input terminal configured to receive a power supply voltage, an output terminal, a switch, a detector, and a controller. The switch is provided between the input terminal and the output terminal. The detector is configured to output a limitation signal without delay when a current flowing through the switch exceeds a prescribed tolerance value. The controller is configured to receive the limitation signal and control the switch to prevent the current from exceeding the tolerance value. The detector is configured output a turn-off signal to the controller when a first state continues for a delay time determined depending on the current's magnitude. The first state is a state where the current is smaller than the tolerance value and the current exceeds a first threshold value smaller than the tolerance value. The controller turns off the switch in response to the turn-off signal.

A voltage tracking circuit includes a first, second, third and fourth transistor. The first transistor is in a first well, the first transistor including a first source terminal and a first body terminal that are coupled to a first voltage supply. The second transistor includes a second source terminal being coupled to the first drain terminal, a second gate terminal being coupled to a pad voltage terminal and configured to receive a pad voltage. The third transistor is in a second well, and includes a third gate terminal coupled to the first voltage supply, and a third body terminal coupled to a first node. The fourth transistor includes a fourth drain terminal coupled to the third source terminal, a fourth gate terminal coupled to the third gate terminal and the first voltage supply, and a fourth source terminal coupled to the pad voltage terminal.

A power clamp circuit includes an electro-static discharge (ESD) current discharge circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage, a first triggering circuit including a first resistor, a first capacitor, and a fourth MOS transistor and configured to trigger the first MOS transistor, a second triggering circuit including a second resistor, a second capacitor, and a fifth MOS transistor and configured to trigger the second MOS transistor, and a third triggering circuit configured to turn off the third MOS transistor during a normal operation and turn on the third MOS transistor when an ESD event occurs.