The present disclosure discloses a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a doped epitaxial layer located on one side of the substrate, a channel layer located on one side of the doped epitaxial layer away from the substrate, a potential barrier layer located on one side of the channel layer away from the doped epitaxial layer, and a first electrode and a second electrode located on one side of the potential barrier layer away from the channel layer, wherein the first electrode penetrates the potential barrier layer, the channel layer and part of the doped epitaxial layer, the first electrode forms a Schottky contact with the channel layer, and a resistance of the part of the doped epitaxial layer in contact with the first electrode is greater than a resistance of the channel layer.

In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer.

Provided are a diode and a manufacturing method therefor. The diode includes: a nitride channel layer; a nitride barrier layer, formed on the nitride channel layer; an oxidation forming layer, wherein a part of the oxidation forming layer is positioned in the nitride barrier layer, and a surface of the oxidation forming layer away from the nitride channel layer is flush with a surface of the nitride barrier layer away from the nitride channel layer; a passivation layer, formed on the nitride barrier layer, wherein the passivation layer includes a first groove penetrating through the passivation layer to expose the oxidation forming layer and a part of the nitride barrier layer; and a first electrode, formed in the first groove, wherein the first electrode is in contact with the nitride barrier layer and the oxidation forming layer.

In one general embodiment, a structure includes a first diode, comprising: a first layer having a first type of dopant, and a second layer above the first layer, the second layer having a second type of dopant that is opposite to the first type of dopant. A second diode is formed directly on the first diode. The second diode comprises a first layer having a third type of dopant and a second layer above the first layer of the second diode, the second layer of the second diode having a fourth type of dopant that is opposite to the third type of dopant. In another general embodiment, a process includes a repeated sequence of growing a first layer having a first type of electrically active dopant and growing a second layer having a second type of electrically active dopant that is opposite to the first type of dopant.

A semiconductor device includes a plurality of tunnel diodes, each of which includes a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type that is provided above the first semiconductor region, the second semiconductor region being a nanowire shape; an insulating film provided around a side surface of the second semiconductor region; a plurality of first electrodes, each coupled to the first semiconductor region; and a plurality of second electrodes, each coupled to the second semiconductor region, wherein the second electrode has a first surface that faces the side surface of the second semiconductor region across the insulating film, and a diameter of a second semiconductor region of a first tunnel diode of the plurality of tunnel diodes is different from a diameter of a second semiconductor region of a second tunnel diode.

One or more systems, devices and/or methods provided herein relate to a device that can facilitate generation of a pulse to affect a qubit and to a method that can facilitate fabrication of a semiconductor device. The semiconductor device can comprise an RTD and an FET co-integrated in a common layer extending along a substrate. A method for fabricating the semiconductor device can comprise applying, at a substrate layer, a template structure comprising an opening, a cavity and a seed structure comprising a seed material and a seed surface, and sequentially growing along the substrate a plurality of diode layers of an RTD and a plurality of transistor layers of an FET within the cavity of the template structure from the seed surface, wherein the RTD and FET are co-integrated along the substrate.

An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.

The present disclosure provides a resonant tunneling diode including: a first barrier layer; a second barrier layer; a potential well layer between the first barrier layer and the second barrier layer, materials of the first barrier layer, the second barrier layer, and the potential well layer including a group III nitride, a material of the potential well layer including a gallium element; a first barrier layer between the first barrier layer and the potential well layer; and/or a second barrier layer between the second barrier layer and the potential well layer.

A method for controlling the carrier concentration of nickel oxide is disclosed. The method for controlling the carrier concentration of nickel oxide comprises the steps of: preparing an n-type gallium oxide substrate on which an n-type gallium oxide epitaxial layer is formed; sputtering a nickel oxide target in a first mixed gas atmosphere of argon and oxygen, thereby depositing a first p-type nickel oxide layer on the n-type gallium oxide epitaxial layer, and sputtering the nickel oxide target in a second mixed gas atmosphere of argon and oxygen, thereby depositing a second p-type nickel oxide layer on the n-type gallium oxide epitaxial layer.

An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.