A 4H-SiC lateral bi-directional JBS diode integrated MOSFET (L-BID-JBSFET). The unit cell of the L-BiD-JBSFET is constructed by connecting two SiC lateral JBSFET unit cells back-to-back with a common-drain configuration. Alternate embodiments include SiC lateral MOSFET and SiC lateral JBSFET devices. A Schottky region can be integrated within a lateral MOSFET cell structure to form the JBSFET.

The present disclosure relates to a semiconductor device, especially for a metal oxide semiconductor field effect transistor (MOSFET), the semiconductor device having RESURF architecture suitable for current switching and signal processing purposes. The advantage of the disclosure is providing a semiconductor cell, especially for a metal oxide semiconductor field effect transistor (MOSFET) with a lower specific on-state resistance and a higher BVdss. Also, very low specific on-state resistances can be achieved with wide cell pitches (1.6 m, for Wd=0.40 m), which improves the dynamic performance and the SOA (safe operating area) capability. The present disclosure also relates to a metal oxide semiconductor field effect transistor (MOSFET), including at least two semiconductor cells connected to each other.

A semiconductor device including a bootstrap diode is provided. The semiconductor device comprises a first deep well region and a second deep well region disposed in a substrate; a pinch-off region disposed between the first and second deep well regions and configured to have a depth smaller than depths of the first and second deep well regions from a top surface of a substrate; a first buried layer and a second buried layer respectively disposed in the first and second deep well regions; a P-type source region and a N-type drain region respectively disposed in the first and second deep well regions; and a N-type sink region surrounding the P-type source region, where the N-type sink region has a doping concentration higher than a doping concentration of the first deep well region.

The semiconductor device includes an n-type first semiconductor region 11 formed on a surface side of a p-type semiconductor substrate 10 and serving as a common path for currents flowing through a switching element and a protection element, an n-type common contact region 12 formed on the first semiconductor region 11 with a high impurity concentration and connected to a common electrode 21 serving as both a first main electrode and a protection element side first electrode, a p-type second semiconductor region 13 and a p-type third semiconductor region 14 locally formed in the first semiconductor region 11 at locations separated from the common contact region 12, and an n-type fourth semiconductor region 15 locally formed in the second semiconductor region 13 in plan view. A second main electrode 22 is connected to the fourth semiconductor region 15, and a protection element side second electrode 26 is provided inside the third semiconductor region 14.

A semiconductor structure includes a region of semiconductor material of a first conductivity type. A doped region of a second conductivity type is within the region of semiconductor material at a first depth. A semiconductor device is in a first portion of the region of semiconductor material and includes a first current carrying region of the second conductivity type and a second current carrying region. A PN diode is in a second portion of the region of semiconductor material and includes a cathode region of the second conductivity type and anode region of the first conductivity type. The cathode region is coupled to the first current carrying region, the anode region is coupled to the doped region, and the doped region is configured to electrically isolate the semiconductor device from region of semiconductor material below the doped region in response to a forward bias applied to the semiconductor device.

The semiconductor device includes an n-type first semiconductor region 11, and an n-type common contact region 12 formed locally with a high impurity concentration on the first semiconductor region 11 and connected to a common electrode that serves as both a first main electrode of a switching element and a protection element side first electrode on the protection element side. A p-type second semiconductor region 13 and an n-type third semiconductor region 14 are provided in a switching element region R1. The p-type second semiconductor region 13 is formed in the first semiconductor region 11 at a location separated in the radial direction from the common contact region 12, and the n-type third semiconductor region 14 is formed in the second semiconductor region 13. A second main electrode is connected to the third semiconductor region 14. A p-type fourth semiconductor region 16 is provided in a protection element region R2. The p-type fourth semiconductor region 16 is formed in the first semiconductor region 11 at a location separated in the radial direction from the common contact region 12. A protection element side second electrode is connected to the fourth semiconductor region 16.