A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.

According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided.

A semiconductor device includes a semiconductor part and first to fourth electrodes. The semiconductor part includes a first layer of a first conductivity type and second and third layers of a second conductivity type. The first and second electrodes are provided on back and front surfaces of the semiconductor part, respectively. The third electrode is provided inside a trench of the semiconductor part. The fourth electrode is provided on the front surface of the semiconductor part. The first layer extends between the first electrode and the second and fourth electrodes. The second layer is provided between the first layer and the second electrode. The third layer is provided between the first layer and the fourth electrode. The third electrode includes an end provided between the third layer and the fourth electrode. The third layer is electrically connected to the second electrode via the third and fourth electrodes.

A silicon-on-insulator (SOI) power device with introduced fixed charges is provided. The SOI power device is a shorted-anodelateral insulated gate bipolar transistor (SA-LIGBT) or separated shorted-anodelateral insulated gate bipolar transistor (SSA-LIGBT) structure, and includes a semiconductor substrate, a dielectric buried layer, and a semiconductor active layer stacked in sequence, where a first charge layer is provided between the dielectric buried layer and the semiconductor active layer, and/or a second charge layer is provided between a field oxide layer and the semiconductor active layer; and the charge layer carries continuously and uniformly distributed positive charges. The snapback present in the output characteristics of the traditional SA-LIGBT or SSA-LIGBT is addressed. By inserting the fixed charges between the dielectric buried layer and the semiconductor active layer, the SOI power device reduces the voltage of the snapback effect and significantly suppresses the occurrence of the snapback phenomenon.

In plan view of an RC-IGBT, a boundary region has an occupancy rate of an n.sup.+-type source layer per unit area, the occupancy rate being smaller than an occupancy rate of the n.sup.+-type source layer per unit area in an IGBT region, and the boundary region has an occupancy rate of a p.sup.+-type contact layer per unit area, the occupancy rate being smaller than an occupancy rate of the p.sup.+-type contact layer per unit area in an IGBT region.

In one aspect, a silicon-on-insulator semiconductor device includes: a substrate; a buried dielectric layer disposed on the substrate; a first electrode; a second electrode; and a drift region disposed on the buried dielectric layer. An upper surface of the drift region forms a drop structure including a first side adjacent to the first electrode, a second side adjacent to the second electrode, and a transition region between the first side and the second side. An upper surface of the second side is higher than a bottom surface of the first side, such that a thickness of the drift region at the second side is greater than that at the first side. The first electrode and the second electrode are configured such that a voltage applied to the second electrode is greater than a voltage applied to the first electrode when a reverse bias voltage is applied to the device.

A semiconductor device includes a semiconductor layer including an element region, and a termination region; a first electrode; a second electrode; a semi-insulating film located on the termination region; an insulating film located between the semiconductor layer and the semi-insulating film; and a protective film located on the semi-insulating film. The insulating film includes an inner perimeter portion, the inner perimeter portion being located between an end portion of the first electrode positioned at the termination region side and an end portion of the second semiconductor part positioned at the termination region side, an outer perimeter portion located between the second electrode and the semiconductor layer, and an intermediate portion located between the inner perimeter portion and the outer perimeter portion. A thickness of the intermediate portion is less than a thickness of the inner perimeter portion and a thickness of the outer perimeter portion.

A semiconductor device includes, within an outer peripheral region: an outer peripheral p-type layer; an outer peripheral n-type layer positioned on an outer peripheral side relative to the outer peripheral p-type layer with a space from the outer peripheral p-type layer; a high breakdown voltage p-type layer arranged to include a portion of an upper surface of a semiconductor substrate located between the outer peripheral p-type layer and the outer peripheral n-type layer; a drift n-type layer extending up to the upper surface between the high breakdown voltage p-type layer and the outer peripheral n-type layer; a protective electrode disposed above the high breakdown voltage p-type layer via an interlayer insulating film and electrically connected to an upper electrode; and a semi-insulating film covering the upper surface between the protective electrode and the outer peripheral n-type layer and having a resistivity of 110.sup.8 .Math.cm to 110.sup.14 .Math.cm at 25 C.