A semiconductor device having a semiconductor substrate that includes first to third epitaxial layers provided sequentially on a starting substrate, the third epitaxial layer forming a pn junction with the second epitaxial layer, and including a plurality of first semiconductor regions formed on a second semiconductor region. The semiconductor device further includes a plurality of trenches penetrating the first and second semiconductor regions to reach the second epitaxial layer, a plurality of gate electrodes provided in the trenches respectively via a gate insulating film, a metal film in ohmic contact with the first semiconductor regions, a first electrode electrically connected to the first semiconductor regions via the metal film, and a second electrode provided at a back surface of the starting substrate. Each of the starting substrate and the first to third epitaxial layers contains silicon carbide. The silicon carbide semiconductor device has a vacancy trap in an entire area of the semiconductor substrate.

The present disclosure provides a semiconductor deposition monitoring device comprising a supporting table, a chamber, a lamp, an optical sensor, a conduit, a plurality of sensors in the conduit, and a heat exchanger. The supporting table supports a deposition target wafer on which a deposition material is deposited. The chamber comprises an upper dome and a lower dome. The lamp emits light to the chamber. The optical sensor receives the irradiated light and measures the deposition material formed in the chamber. The conduit has an inlet conduit through which air is injected into the chamber and an outlet conduit through which the air is discharged from the chamber. The plurality of sensors sense information of the air. The sensed information may be used to control the heat exchanger.

Provided is a method of producing an epitaxial silicon wafer, which is excellent in productivity and prevents the formation of a backside haze in consecutive single-wafer processing epitaxial growth procedures on a plurality of silicon wafers without cleaning a process chamber after each epitaxial growth procedure. The method of producing an epitaxial silicon wafer includes: a step of loading a silicon wafer; a step of forming a silicon epitaxial layer; a step of unloading the silicon wafer; and a cleaning step. The cleaning step is performed before and after repeating a predetermined number of times a series of growth procedures including the silicon wafer loading step, the silicon epitaxial layer formation step, and the silicon wafer unloading step.

A method of forming a semiconductor device comprises forming a fin structure; forming a source/drain structure in the fin structure; and forming a gate electrode over the fin structure. The source/drain structure includes Si.sub.−x−yM1.sub.xM2.sub.y, where M1 includes Sn, M2 is one or more of P and As, 0.01≤x≤0.1, and 0.01≤y≤0.

A plasma processing apparatus is provided. The plasma processing apparatus includes a processing chamber defining a vertical direction and a lateral direction. The plasma processing apparatus includes a pedestal disposed within the processing chamber. The pedestal is configured to support the substrate. The plasma processing apparatus includes a radio frequency (RF) disposed within the processing chamber. The RF bias electrode defines a RF zone extending between a first end of the RF bias electrode and a second end of the RF bias electrode along the lateral direction. The plasma processing apparatus includes a focus ring disposed within the processing chamber. The plasma processing apparatus further includes a focus ring adjustment assembly. The focus ring adjustment assembly includes a lift pin positioned outside of the RF zone. The lift pin is movable along the vertical direction to adjust a distance between the pedestal and the focus ring along the vertical direction.

Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.

A sintered oxide includes an In.sub.2O.sub.3 crystal, and a crystal A whose diffraction peak is in an incidence angle (2θ) range defined by (A) to (F) below as measured by X-ray (Cu-K α ray) diffraction measurement: 31.0 to 34.0 degrees . . . (A); 36.0 to 39.0 degrees . . . (B); 50.0 to 54.0 degrees . . . (C); 53.0 to 57.0 degrees . . . (D); 9.0 to 11.0 degrees . . . (E); and 19.0 to 21.0 degrees . . . (F).

A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

A method of forming a semiconductor device comprises forming a fin structure; forming a source/drain structure in the fin structure; and forming a gate electrode over the fin structure. The source/drain structure includes Si.sub.1−x−yM1.sub.xM2.sub.y, where M1 includes Sn, M2 is one or more of P and As, 0.01≤x≤0.1, and 0.01≤y≤0.