A compound semiconductor has a high electron concentration of 510.sup.19 cm.sup.3 or higher, exhibits an electron mobility of 46 cm.sup.2/V.Math.s or higher, and exhibits a low electric resistance, and thus is usable to produce a high performance semiconductor device. The present invention provides a group 13 nitride semiconductor of n-type conductivity that may be formed as a film on a substrate having a large area size at a temperature of room temperature to 700 C.

A focus ring adjustment assembly of a system for processing workpieces under vacuum, where the focus ring may include a lower side having a first surface portion and a second surface portion, the first surface portion being vertically above the second surface portion. The adjustment assembly may include a pin configured to selectively contact the first surface portion of the focus ring, and an actuator operable to move the pin along the vertical direction between an extended position and a retracted position. The extended position of the pin may be associated with the distal end of the pin contacting the first surface of the focus ring and the focus ring being accessible for removal by a workpiece handling robot from the vacuum process chamber.

A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.

A substrate processing system, including a processing module having at least one sputtering source; a first buffer module positioned on a first side of the processing module; a second buffer module positioned on a second side of the processing module directly opposite the first side; a first cooling module attached to the first buffer module; a second cooling module attached to the second buffer module; a transport system transporting substrate carriers in a straight line through the first cooling module, the first buffer module, the processing module, the second buffer module and the second cooling module; wherein the system is arranged linearly in the order: first cooling module, the first buffer module, the processing module, the second buffer module and the second cooling module.

Provided is a method for forming an epitaxial layer at a low temperature. The method for forming the epitaxial layer includes transferring a substrate into an epitaxial chamber and performing an epitaxial process on the substrate to form an epitaxial layer on the substrate. The epitaxial process includes heating the substrate at a temperature of about 700 C. or less and injecting a silicon gas into the epitaxial chamber in a state in which the inside of the epitaxial chamber is adjusted to a pressure of about 300 Torr or less to form a first epitaxial layer, stopping the injection of the silicon gas and injecting a purge gas into the epitaxial chamber to perform first purge inside the epitaxial chamber, heating the substrate at a temperature of about 700 C. or less and injecting the silicon gas into the epitaxial chamber in the state in which the inside of the epitaxial chamber is adjusted to a pressure of about 300 Torr or less to form a second epitaxial layer, and stopping the injection of the silicon gas and injecting the purge gas into the epitaxial chamber to perform second purge inside the epitaxial chamber.

A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si.sub.1-y-a-bGe.sub.aSn.sub.bM2.sub.y, wherein 0<a, 0<b, 0.01(a+b)0.1, 0.01y0.1, and M2 is P or As.

A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si.sub.1xyM1.sub.xM2.sub.y, where M1 includes Sn, M2 is one or more of P and As, and 0.01x0.1, and 0.01y0.1.

A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

There is provided a hard mask formed on a substrate for manufacturing a semiconductor device, the hard mask including a film made of a compound which is composed of Ru and an element selected from Ti, Zr, Hf, V, Nb, Ta, Mo, W, and Si.